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may 2009 i ? 2009 actel corporation see the actel website for the latest version of the datasheet. v5.4 rtax-s/sl radtolerant fpgas radiation performance ? seu-hardened registers eliminate the need for triple- module redundancy (tmr) ? immune to single-event upsets (seu) to let th > 37 mev-cm 2 /mg ?seu rate < 10 -10 errors/bit-day in worst-case geosynchronous orbit ? expected sram upset rate of <10 -10 errors/bit-day with use of error detection and co rrection (edac) ip (included) with integrated sram scrubber ? single-bit correction, double-bit detection ? variable-rate background refreshing ? total ionizing dose up to 300 krad (si, functional) ? single-event latch-up immunity (sel) to let th > 117 mev- cm 2 /mg ? tm1019 test data available ? single event transient (set) ? no anomalies up to 150 mhz processing flows ? b-flow ? mil-std-883b ? e-flow ? actel extended flow ? ev-flow ? class v equivalent flow processing consistent with mil-prf 38535 prototyping options ? commercial axcelerator devices for functional verification ? rtax-s proto devices with same functional and timing characteristics as flight unit in a non-hermetic package ? low priced reprogrammable proasic ? 3 option for functional verification rtax-sl low power option ? offers approximately half the standby current of the standard rtax-s device at worst-case conditions leading-edge performance ? high-performance embedded fifos ? 350+ mhz system performance ? 500+ mhz internal performance ? 700 mb/s lvds capable i/os specifications ? up to 4 million equivale nt system gates or 500 k equivalent asic gates ? up to 20,160 seu-hardened flip-flops ? up to 840 i/os ? up to 540 kbits embedded sram ? manufactured on advanced 0.15 m cmos antifuse process technology, 7 layers of metal ? electrostatic discharge (esd) is 2,000 v (hbm mil-std-883, tm3015) features ? single-chip, nonvolatile solution ? 1.5 v core voltage for low power ? flexible, multi-standard i/os: ? 1.5 v, 1.8 v, 2.5 v, 3.3 v mixed voltage operation ? bank-selectable i/os ? 8 banks per chip ? single-ended i/o standards: lvttl, lvcmos, 3.3 v pci ? jtag boundary scan testi ng (as per ieee 1149.1) ? differential i/o standa rds: lvpecl and lvds ? voltage-referenced i/o stan dards: gtl+, hstl class 1, sstl2 class 1 and 2, sstl3 class 1 and 2 ? hot-swap compliant with cold-sparing support (except pci) ? embedded memory with va riable aspect ratio and organizations: ? independent, width-configurable read and write ports ? programmable embedded fifo control logic ? rom emulation capability ? deterministic, user-controllable timing ? unique in-system diagnostic and debug capability table 1 ? rtax-s/sl family product profile device rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl capacity equivalent system gates asic gates 250,000 30,000 1,000,000 125,000 2,000,000 250,000 4,000,000 500,000 modules register (r-cells) combinatorial (c-cells) flip-flops (maximum) 1,408 2,816 2,816 6,048 12,096 12,096 10,752 21,504 21,504 20,160 40,320 40,320 embedded ram/fifo (without edac) core ram blocks core ram bits (k = 1,024) 12 54 k 36 162 k 64 288 k 120 540 k clocks (segmentable) hardwired routed 4 4 4 4 4 4 4 4 i/os i/o banks user i/os (maximum) i/o registers 8 198 744 8 418 1,548 8 684 2,052 8 840 2,520 package ccga/lga cqfp 624 208, 352 624 352 624, 1152 256, 352 1272 352 v5.4
rtax-s/sl radtolerant fpgas ii v5.4 ordering information temperature grade offerings package rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl cq208 b, e, ev ? ? ? cq256 ? ? b, e, ev ? cq352 b, e, ev b, e, ev b, e, ev b, e, ev cg624/lg624 b, e, ev b, e, ev b, e, ev ? cg1152/lg1152 ? ? b, e, ev ? cg1272/lg1272 ? ? ? b, e, ev note: b = mil-std-883 class b e = e-flow (actel space-level flow) ev = actel "v" equivalent flow (class v processing consistent with mil-prf 38535) rtax2000 s / s l1 cgs _ part num b er s pee d g ra d e blank = s tan d ar d s pee d = approximately 15% faster than s tan d ar d (applies to rtax250 s / s l, rtax1000 s / s l. rtax2000 s / s l) 1 = approximately 10% faster than s tan d ar d (applies to rtax4000 s / s l) 1 pa c ka g e type c q = c erami c qua d flat pa c k cg = c erami c c olumn g ri d array l g = = lan d g ri d array 6 24 b pa c ka g e lea d c ount appli c ation b = mil- s td 883 c lass b e = e-flow (a c tel s pa c e-level flow) ev = c lass v e q uivalent flow pro c essin g c onsistent with mil-prf 38535 rtax1000 s / s l 1,000,000 e q uivalent s ystem g ates = rtax250 s / s l 250,000 e q uivalent s ystem g ates = s s tan d ar d family = s l low-power option = rtax2000 s / s l 2,000,000 e q uivalent s ystem g ates = note: proto refers to the rtax- s / s l prototype units. all ccg a proto units will b e offere d with the s ix s i g ma c olumn. s s ix s i g ma c olumn rtax4000 s / s l 4,000,000 e q uivalent s ystem g ates =
rtax-s/sl radtolerant fpgas v5.4 iii speed grade and temperature grade matrix device resources i/os per package rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl std ???? -1 ???? notes: 1. data applies to b,e,ev flow devices. 2. contact your actel repres entative for availability. user i/os (including clock buffers) device rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl cq208 115 ? ? ? cq256 ??136? cq352 198 198 198 166 cg624/lg624 232 418 418 ? cg1152/lg1152 ??684? cg1272/lg1272 ???840 note: cqfp = ceramic quad flat pack and ccga = ceramic column grid array, lga = land grid array package device single-ended differential pair pair total i/os cq208 rtax250s 7 41 13 115 cq256 rtax2000s 4 66 0 136 cq352 rtax250s 2 98 0 198 rtax1000s 2 98 0 198 rtax2000s 2 98 0 198 rtax4000s 4 81 0 166 cg624 rtax250s 0 124 0 248 rtax1000s 68 170 5 418 rtax2000s 52 178 5 418 cg1152 rtax2000s 0 342 0 684 cg1272 rtax4000s 0 420 0 840
rtax-s/sl radtolerant fpgas iv v5.4 actel mil-std-883 class b product flow table 2 ? actel mil-std-883 class b product flow for rtax-s/sl 1, 2 step screen method requirement 1 internal visual 2010, condition b 100% 2 serialization 100% 3 temperature cycling 1010, condition c, 10 cycles minimum 100% 4 constant acceleration 2001, y1 orientation only condition b for cq352, lg624, lg1152 condition d for cq208 condition a 3 for lg1272, cq352 100% 5 particle impact noise detection 2020, condition a 100% 6 seal (fine & gross leak test) 1014 100% 7 pre-burn-in electrical parameters in acco rdance with applicable actel device specification 100% 8 dynamic burn-in 1015, condition d, 160 hours at 125c or 80 hours at 150c minimum 100% 9 interim (post-burn-in) electrical parameters in accordance with ap plicable actel device specification 100% 10 percent defective allowable (pda) calculation 5% all lots 11 final electrical test 2 a. static tests (1) 25c (2) ?55c and +125c b. functional tests (1) 25c (2) ?55c and +125c c. switching tests at 25c in accordance with ap plicable actel device specification, which includes a, b, and c: 5005, table 1, subgroup 1 5005, table 1, subgroup 2, 3 5005, table 1, subgroup 7 5005, table 1, subgroup 8a, 8b 5005, table 1, subgroup 9 100% 12 external visual 2009 100% notes: 1. for ccga devices, all assembly , screening, and tci testing are performed at lga level. only qa electrical and mechanical visu al are performed after solder column attachment. 2. rtax-s and rtax-sl devices have the same s ilicon and are distinguished by screening the i cca current limits at 125c final electrical test. 3. condition a applies to rtax4000s/sl packages only.
rtax-s/sl radtolerant fpgas v5.4 v actel extended flow table 3 ? actel extended flow for rtax-s/sl 1, 2, 3, 4 step screen method requirement 1 destructive bond pull 5 2011, condition d extended sample 2 internal visual 2010, condition a 100% 3 serialization 100% 4 temperature cycling 1010, condition c, 10 cycles minimum 100% 5 constant acceleration 2001, y1 orientation only condition b for cq352, lg624, lg1152 condition d for cq208 condition a 5 for lg1272, cq352 6 particle impact noise detection 2020, condition a 100% 7 radiographic (x-ray) 2012, one view (y1 orientation) only 100% 8 pre-burn-in electrical parameters in acco rdance with applicable actel device specification 9 dynamic burn-in 1015, condition d, 240 hours at 125c or 120 hours at 150c minimum 100% 10 interim (post-dynamic -burn-in) electrical parameters in accordance with ap plicable actel device specification 100% 11 static burn-in 1015, condition c, 72 hours at 150c or 144 hours at 125c minimum 100% 12 interim (post-static-burn-in) electrical parameter s in accordance with ap plicable actel device specification 100% 13 percent defective allowable (pda) calculation 5% overall, 3% functional parameters at 25c all lots 14 final electrical test 4 a. static tests (1) 25c (2) ?55c and +125c b. functional tests (1) 25c (2) ?55c and +125c c. switching tests at 25c in accordance with ap plicable actel device specification, which includes a, b, and c: 5005, table 1, subgroup 1 5005, table 1, subgroup 2, 3 5005, table 1, subgroup 7 5005, table 1, subgroup 8a, 8b 5005, table 1, subgroup 9 100% 15 seal (fine & gross leak test) 1014 100% 16 external visual 2009 100% notes: 1. actel offers extended flow for users requ iring additional screening beyond mil-std-8 33, class b requirement. actel is offerin g this extended flow incorporating the majority of the screening pr ocedures as outlined in method 5004 of mil-std-883, class s. 2. the quality conformance inspec tion (qci) for extended flow devices still comply to mil-std-833, class b requirement. 3. for ccga devices, all assembly/screening/t ci testing are performed at lga level. only qa electrical and mechanical visual are performed after solder column attachment. 4. rtax-s and rtax-sl devices have the same s ilicon and are distinguished by screening the i cca current limits at 125c final electrical test. 5. condition a applies to rtax4000s/sl packages only. 6. requirement for 100% nondestructive bond pull per method 2003 is substituted by an extensive destructive bond pull to method 2011 condition d on an extended sample basis.
rtax-s/sl radtolerant fpgas vi v5.4 actel "ev" flow (class v flow equivalent processing) table 4 ? actel "ev" flow (class v equivalen t flow processing) for rtax-s/sl 1, 2, 3 step screen method requirement 1 destructive bond pull 4 2011, condition d extended sample 2 internal visual 2010, condition a 100% 3 serialization 100% 4 temperature cycling 1010, condition c, 50 cycles minimum 100% 5 constant acceleration 2001, y1 orientation only condition b for cq352, lg624, lg1152 condition d for cq208 condition a 5 for lg1272, cq352 100% 6 particle impact noise detection 2020, condition a 100% 7 radiographic (x-ray) 2012, one view (y1 orientation) only 100% 8 pre-burn-in electrical parameters in acco rdance with applicable actel device specification 100% 9 dynamic burn-in 1015, condition d, 240 hours at 125c or 120 hours at 150c minimum 100% 10 interim (post-dynamic-bur n-in) electrical parameters in accordance with applicable actel device specification 100% 11 static burn-in 1015, condition c, 72 hours at 150c or 144 hours at 125c minimum 100% 12 interim (post-static-burn-in) electrical parameter s in accordance with applicable actel device specification 100% 13 percent defective allowable (pda) calculation 5% overall, 3% functional parameters at 25c all lots 14 final electrical test 3 a. static tests (1) 25c (2) ?55c and +125c b. functional tests (1) 25c (2) ?55c and +125c c. switching tests at 25c in accordance with applicable actel device specification, which includes a, b, and c: 5005, table 1, subgroup 1 5005, table 1, subgroup 2, 3 5005, table 1, subgroup 7 5005, table 1, subgroup 8a, 8b 5005, table 1, subgroup 9 100% 15 seal (fine & gross leak test) 1014 100% 16 external visual 2009 100% 17 wafer lot specific life test (group c) mil-prf-38535, appendix b, sec. b.4.2.c all wafer lots notes: 1. actel offers "ev" flow for user s requiring full compli ance to mil-prf-3853 5 class v requirement. the "ev" process flow is expanded from the existing e-flow requirement (it still meet s the full smd requirement for current e-f low devices) with the intention to be in full compliance to mil-pr f-38535 table ia and appendix b requirement, but without the offi cial class v certification from dscc. 2. for ccga devices, all assembly/screening/t ci testing are performed at lga level. only qa electrical and mechanical visual are performed after solder column attachment. 3. rtax-s and rtax-sl devices have the same s ilicon and are distinguished by screening the i cca current limits at 125c final electrical test. 4. condition a applies to rtax4000s/sl packages only. 5. requirement for 100% nondestructive bond pull per method 2003 is substituted by an extensive destructive bond pull to method 2011 condition d on an extended sample basis.
v5.4 vii table of contents rtax-s/sl radtolerant fpgas general description device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 programmable interconnect element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 global resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 design environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 low-cost prototyping solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 in-system diagnostic and debug capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 detailed specifications operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 routing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 global resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 other architectural features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102 package pin assignments 208-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 256-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -4 352-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -8 624-pin ccga/lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 1152-pin ccga/lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 1272-pin ccga/lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 international traffic in arms regulations (itar) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 actel safety critical, life support, and high-re liability applications policy . . . . . 4-7

rtax-s/sl radtolerant fpgas v5.4 1-1 general description rtax-s/sl offers high performance at densities of up to four million equivalent syst em gates for space-based applications. based upon the actel commercial axcelerator ? family, rtax-s/sl has several system-level features such as embedded sram (with built-in fifo control logic), segmentable clocks, chip-wide highway routing, and carry logic. featuring seu-hardened flip-flops that offer the benefits of user-implemented triple module redundancy (tmr) without the associated overhead, the rtax-s/sl family is the second generation actel product offering for space applications. the rtax-s/ sl devices are manufactured using a 0.15 m technology at a umc facility in taiwan. these devices offer levels of radiation survivability far in excess of typical cmos devices. device architecture actel rtax-s/sl architecture, derived from the highly- successful a54sx-a sea-of-m odules architecture, has been designed for high performance and total logic module utilization ( figure 1-1 ). unlike traditional fpgas, the entire floor of the rtax-s/sl device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. programmable interconnect element the rtax-s/sl family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal ( figure 1-2 on page 1-2 ). this completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional fpgas) and enables the efficient sea-of -modules arch itecture. the antifuses are normally open circuit and, when programmed, form a permanent, passive, low- impedance connection, lead ing to the fastest signal propagation in the industry. in addition, the extremely small size of these interconnect elements gives the rtax-s family abundant routing resources. figure 1-1 ? sea-of-modules comparison switch matrix routing logic block logic modules sea-of-modules architecture traditional fpga architecture
rtax-s/sl radtolerant fpgas 1-2 v5.4 the very nature of actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (fuselock ? technology). cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. reverse engineering is virtually imposs ible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "security" on page 2-101 ). actel's rtax-s/sl family provides two types of logic modules: the register cell (r -cell) and the combinatorial cell (c-cell). the rtax-s/sl c-cell can implement more than 4,000 combinatorial functi ons of up to five inputs ( figure 1-3 on page 1-3 ). the c-cell contains carry logic for even more efficient im plementation of arithmetic functions. with its small size, the c-cell structure is extremely synthesis-friendly , simplifying the overall design as well as reducing design time. while each seu-hardened r-cell appears as a single d-type flip-flop to the user, each is implemented in silicon using triple redundancy to achieve a let threshold of greater than 60 mev-mg/cm 2 . each tmr r-cell consist of three master-slave latch pairs, each with asynchronous self-correcting feedback paths. the output of each latch on the master or slave side votes with the outputs of the other two latches on that side. if one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents that change from feeding back and permanently latching. care was also taken in the layout to ensu re that a single ion strike could not affect more than one latch (see "r-cell" on page 2-66 for more details). the r-cell contains a flip-f lop featuring asynchronous clear, asynchronous preset, a nd active-low enable control signals ( figure 1-3 on page 1-3 ). the r-cell registers feature programmable clock polarity selectable on a register-by-register basis. this provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the fpga) while conservi ng valuable clock resources. the clock source for the r-cell can be chosen from the hardwired clocks, routed cloc ks, or internal logic. two c-cells, a single r-cell, and two transmit (tx) and two receive (rx) routing buffers form a cluster, while two clusters comprise a supercluster ( figure 1-4 on page 1-3 ). each supercluster also contains an independent buffer (b) module, which supports buffer insertion on high-fanout nets by the place-and-rout e tool, minimizing system delays while improving logic utilization. the logic modules within th e supercluster are arranged so that two combinatorial modules are side-by-side, giving a c?c?r ? c?c?r pattern to the supercluster. this c?c?r pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance ( figure 1-5 on page 1-3 ). the rtax-s/sl architecture is fully fracturable, meaning that if one or more of the logic modules in a supercluster are used by a particular signal path, the other logic modules are still available for use by other paths. figure 1-2 ? rtax-s/sl family in terconnect elements
rtax-s/sl radtolerant fpgas v5.4 1-3 figure 1-3 ? rtax-s/sl c-cell and r-cell figure 1-4 ? rtax-s/sl supercluster figure 1-5 ? rtax-s/sl two-bit carry logic a[0:1] b[0:1] d[0:3] db cfn fci fco y c-cell pre clr d e clk q (positive edge triggered) c-cell r-cell rx tx b c r c c c r rx rx rx tx tx tx dcout y y c-cell c-cell carry logic fci fco
rtax-s/sl radtolerant fpgas 1-4 v5.4 at the chip level, superclust ers are organized into core tiles, which are arrayed to build up the full chip. for example, the rtax1000s/sl is composed of a 33 array of nine core tiles. surrounding the array of core tiles are blocks of i/o clusters and the i/o bank ring ( table 1-1 ). each core tile consists of an array of 336 superclusters and four sram blocks (176 superclusters and three sram blocks for the rtax250s /sl). the sram blocks are arranged in a column on the west side of the tile ( figure 1-6 ). table 1-1 ? number of core tiles per device device number of core tiles rtax250s/sl 4 smaller tiles rtax1000s/sl 9 regular tiles rtax2000s/sl 16 regular tiles rtax4000s/sl 30 regular tiles figure 1-6 ? rtax-s/sl device architecture (rtax1000s/sl shown) chip layout supercluster i/o structure ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc s c sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc core tile 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo rx tx b c r c c c r rx rx rx tx tx tx
rtax-s/sl radtolerant fpgas v5.4 1-5 embedded memory as mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded sram blocks along the west side, and each variable-aspect- ratio sram block is 4,608 bits in size. available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. the individual blocks have separate read and write ports that can be configured with different bit widths on each port. for example, data can be written in by eight and read out by one. in addition, every sram bl ock has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fifo without using core logic modules. the fifo width and depth are programmable. the fifo al so features programmable almost-empty (aempty) and almost-full (afull) flags in addition to the normal empty and full flags. in addition to the flag logic, the embedded fifo control unit also contains the counters necessary for the generation of the read and wr ite address pointers as well as control circuitry to prevent metastability and erroneous operation. the embedded sram/fifo blocks can be cascaded to creat e larger configurations. the fifo control unit was not implemented with seu- hardened registers. designs requiring high seu tolerance should implement the fifo control unit from hardened core logic. sram structures are inherently susceptible to upsets caused by high-energy particles encountered in space. high-energy particles can cause an sram cell to change state, resulting in the loss or corruption of a valuable data bit. actel has enhanced the seu tolerance of the embedded sram within rtax-s/sl by employing the use of two upset-mitigation techniques: ? actel has developed error detection and correction (edac) ip for use with rtax-s/sl. edac can be accomplished by the use of smartgen-generated error correcting codes (ecc) ip, which employs the use of shortened hamming codes ? a background memory-refresher, or scrubber circuitry, which has been embedded into the edac ip. the embedded scrubber circuitry periodically refreshes memory in the background to ensure that no data corruption occurs while the memory is not in use. the use of edac ip comb ined with the embedded memory scrubber circuitry, gives the rtax-s/sl an seu radiation performance level of better than 10 -10 errors/ bit-day. see the application note using edac ram for radtolerant rtax-s/sl fpgas and axcelerator fpgas . i/o logic the rtax-s/sl family of fpgas features a flexible i/o structure, supporting a range of mixed voltages with its bank-selectable i/os: 1.5 v, 1.8 v, 2.5 v, and 3.3 v. in all, rtax-s/sl fpgas support at least 14 different i/o standards (single-ended, differential, voltage- referenced). the i/os are organized into banks, with eight banks per device (two per side). the configuration of these banks determines the i/o standa rds supported (see "user i/os" on page 2-12 for more information). all i/o standards are available in each bank. each i/o module has an input re gister (inreg), an output register (outreg), and an enable register (enreg) ( figure 1-7 on page 1-6 ). an i/o cluster includes two i/o modules, four rx modules, two tx modules, and a buffer (b) module. by design, all user flip-flo ps in the rtax-s fpgas are immune to seus including the following three registers located in every i/o cell buffer: inreg, outreg, and enreg. routing the rtax-s/sl hierarchical routing structure ties the logic modules, the embedded memo ry blocks, and the i/o modules together ( figure 1-8 on page 1-6 ). at the lowest level, in and between superclu sters, there are three local routing structures: fastconnect, directconnect, and carryconnect routing. directconnects provide the highest performance routing inside the superclusters by connecting a c-cell to the ad jacent r-cell. directconnects do not require an antifuse to make the connection and achieve a signal propagation ti me of less than 0.1 ns. fastconnects provide high-performance, horizontal routing inside the supercluster and vertical routing to the supercluster immediately below it. only one programmable connection is used in a fastconnect path, delivering a maximum routing delay of 0.4 ns. carryconnects are used for routing carry logic between adjacent superclusters. they connect the carry-logic fco output of one c-cell pair to the carry-logic fci input of the c-cell pair of the supercluster below. carryconnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. the next level contains the co re tile routing. over the superclusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. at the chip level, vertical and horizontal tracks extend across the fu ll length of the device, both north-to-south and east-to -west. these tracks are composed of highway routing that extend the entire length of the device (segment ed at core tile boundaries) as well as segmented routi ng of varying lengths.
rtax-s/sl radtolerant fpgas 1-6 v5.4 figure 1-7 ? i/o cluster arrangement figure 1-8 ? rtax-s/sl routing structures i/o cluster i/o module coretile 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo outreg enreg inreg i/o module i/o module rx rx rx rx tx tx b n i o b a k
rtax-s/sl radtolerant fpgas v5.4 1-7 global resources each family member has three types of global signals available to the designer: hclk, clk, and gclr/gpset. there are four hardwired cloc ks (hclk) per device that can directly drive the clock input of each r-cell. each of the four routed clocks (clk ) can drive the clock, clear, preset, or enable pin of an r-cell or any input of a c-cell ( figure 1-3 on page 1-3 ). both these clocks can be segmented, allowing significantly more than eight clock domains to be implemented in the devices. the rtax1000s/sl, rtax2000s/sl, and rtax4000s/sl devices have 12 hclk segments per tile and 28 rclk segments per tile. the rtax 250s/sl has 8 hclk segments per tile and 22 rclk segments per tile. global clear (gclr) and global preset (gpset) drive the clear and preset i nputs of each r-cell as well as each i/o register on a chip-wide basis at power-up. design environment the rtax-s/sl family of fpgas is fully supported by both actel libero ? integrated design environment (ide) and designer fpga development software. actel libero ide is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment (see the libero ide flow diagram located on the actel website). libero ide includes synplify ? ae from synplicity ? , viewdraw ? ae from mentor graphics ? , model sim ? hdl simulator from mentor graphics, waveformer lite? ae from synapticad ? , and designer software from actel. actel's designer software is a place-and-route tool and provides a comprehensive suit e of backend support tools for fpga development. the designer software includes the following: ? timer ? a world-class integr ated static timing analyzer and constraints editor which support timing-driven place-and-route ? netlistviewer ? a design netlist schematic viewer ? chipplanner ? a graphical fl oorplanner viewer and editor ? smartpower ? allows the designer to quickly estimate the power consumption of a design ? pineditor ? a graphical ap plication for editing pin assignments and i/o attributes ? i/o attribute editor ? di splays all assigned and unassigned i/o macros and their attributes in a spreadsheet format with the designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. additionally, the actel back- annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, the actel integrated verification and logic analysis tool. another tool included in the designer software is the smartgen core generator, which easily creates popular an d commonly used logic functions for implementation into your schematic or hdl design. actel designer software is compatible with the most popular fpga design entry and verification tools from eda vendors, such as ment or graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. programming programming support is provided through actel silicon sculptor 3, a single-site programmer driven via a pc-based gui. factory program ming is available for high- volume production needs. low-cost prototyping solutions since the enhanced radiation characteristics of radiation- tolerant devices are not required during the prototyping phase of the design, actel has developed two prototyping options for rtax-s/sl. for early design development and functional verification, ac tel offers the commercial axcelerator devices while for fi nal flight design verification in hardware, actel offers the rt ax-s proto device that has the same form, fit, and function as the flight silicon. prototyping with axcelerator units the prototyping solution usin g the commercial axcelerator devices consists of two parts: ? a well-documented design flow that allows the customer to target an rtax-s/sl design to the equivalent commercial axcelerator device ? a set of actel extender circuit boards that map the commercial device package to the appropriate rtax-s package footprint this methodology provides th e user with a cost-effective solution while maintaining the short time-to-market associated with actel fpgas. prototyping with rtax-s proto units the rtax-s proto units offer a prototyping solution that can be used for final timing verification of the flight design. the rtax-s proto prototype units have the same timing attributes as the rtax-s/sl flight units. prototype units are offered in non-hermetic ceramic packages. the prototype unit s include "proto" in their part number, and ?proto? is marked on devices to indicate that they are not in tended for space flight. they
rtax-s/sl radtolerant fpgas 1-8 v5.4 also are not intended for a pplications, which require the quality of space-flight unit s, such as qu alification of space-flight hardware. rt-proto units offer no guarantee of hermeticit y, and no mil-std-883b processing. at a minimum, users should plan on using class b level devices for all qualification activities. the rt-proto units are electrically tested in a manner to guarantee their performanc e over the full military temperature range. the rt-proto units will also be offered in -1 or standard sp eed grades, so as to enable customers to validate the timi ng attributes of their space designs using actual flight silicon. prototyping with proasic3e reprogrammable units using actel?s proasic3e prot otyping solution offers the unique advantage of reprogrammability, resulting in cost savings while providing fast er functional verification of designs in prototype stage. this methodology employs a footprint compatible adaptor board and an edif netlist and pinout convertor for easy migration. please see the application note prototyping for rtax-s and rtax-sl devices for more details. in-system diagnostic and debug capabilities the rtax-s/sl family of fpgas includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the fpga without disturbing normal device operation. up to four individual signals can be brought out to dedicated probe pins (pra/b/c/d) on the device. the probe circuitry is accessed and controlled via silicon explorer ii ( figure 1-9 ), the actel integrated verification and logic analysis tool that attaches to the serial port of a pc and co mmunicates with the fpga via the jtag port (see "silicon explorer ii probe interface" on page 2-102 ). in addition, actel offers a configurable logic analyzer module (clam), which allows a real-time verification and debug capability to be embedded into ip programmed into actel fpgas. clam allows signals from the inside of the ip core to be routed to the exterior of the chip for verification purposes. summary the actel rtax-s/sl family of fpgas extends the successful rtsx-su family of radiation-tolerant fpgas, adding embedded ram, fifos, and high-speed i/os. with the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an rtax-s/sl design yet still achieve high performance and efficient device utilization in an seu- hardened device. note: *refer to the "pin descriptions" on page 2-11 for more information. figure 1-9 ? probe setup serial connection additional 14 channels (logic analyzer) rtax-s/sl fpgas silicon explorer ii 16-pin connection 22-pin connection ch3/prc* ch4/prd* tdi* tck* tms* pra* prb* tdo*
rtax-s/sl radtolerant fpgas v5.4 1-9 related documents application notes simultaneous switching no ise and signal integrity http://www.actel.com/d ocuments/ssn_an.pdf differences between rtax-s/sl and axcelerator http://www.actel.com /documents/rtaxs_ax_features_an.pdf using edac ram for radtolerant rtax-s/sl fpgas and axcelerator fpgas http://www.actel.com/d ocuments/edac_an.pdf prototyping for rtax-s and rtax-sl devices http://www.actel.com/documen ts/prototypingrtaxs_an.pdf implementation of security in actel antifuse fpgas http://www.actel.com /documents/antifuse_security_an.pdf actel cqfp to fbga adapter socket instructions http://www.actel.com/doc uments/ccga_fbga_an.pdf actel ccga to fbga adapter socket instructions http://www.actel.com/documen ts/cq352-fpga_adapter_an.pdf ieee standard 1149.1 (jtag) in the axcelerator family http://www.actel.com/doc uments/ax_jtag_an.pdf user?s guides and manuals antifuse macro library guide http://www.actel.com/d ocuments/libguide_ug.pdf smartgen, flashrom, analog system builder, and flash memory system builder user?s guide http://www.actel.com/docum ents/smarttime_ug.pdf silicon sculptor user?s guide http://www.actel.com /documents/silisculptii_sculpt3_ug.pdf silicon explorer ii user?s guide http://www.actel.com/doc uments/silexpl_ug.pdf white papers design security in nonvolatile flash and antifuse fpgas http://www.actel.com/documen ts/designsecurity_wp.pdf understanding actel antifuse device security http://www.actel.com/documen ts/antifusesecuritywp.pdf rtax-s/sl testing and reliability update http://www.actel.com/documen ts/rtaxs_rel_test_wp.pdf miscellaneous libero ide flow diagram http://www.actel.com/produ cts/software/libero/#flow

rtax-s/sl radtolerant fpgas v5.4 2-1 detailed specifications 5 v tolerance 3.3 v pci and 3.3 v lvttl (w ith clamp diode enabled) i/o standards directly allow 5 v tolerance. for example, the 3.3v pci i/o standard provides an internal clamp diode between the input pad and the v cci pad so that the voltage at the input pin is clamped below the absolute maximum input voltage of 4.1 v ( table 2-2 on page 2-2 ). an example of the input pad voltage level is shown in eq 2-1 : v input = v cci + v diode = 3.3 v + 0.7 v = 4.0 v eq 2-1 the internal clamp diode is only enabled while the device is powered on, so the voltage at the input will not be clamped if the v cci is powered off. an external series resistor (~100 ) is required between the input pin and the 5 v signal source to limit the current to less than 20 ma ( figure 2-1 ). the 100 resistor was chosen to meet the input tr/tf requirement ( table 2-20 on page 2-22 ). 5 v tolerance is not allowable for v cci greater than 3.3 v or for input signals greater than 5.0 v. table 2-1 ? i/o features comparison i/o assignment clamp diode hot insertion / cold sparing 5v tolerance input buffer output buffer 3.3 v lvttl yes 1 no yes 1 enabled/disabled 3.3 v pci yes no yes 2 enabled/disabled lvcmos2.5 v no yes no enabled/disabled lvcmos1.8 v no yes no enabled/disabled lvcmos1.5 v (jesd8-11) no yes no enabled/disabled voltage-referenced input buffer no yes no enabled/disabled differential, lvds/lvpecl, input no yes no enabled disabled 3 differential, lvds/lvpecl, output no yes no disabled enabled 4 notes: 1. default setting for the clamp diode is set to be pci. the lvttl clamp diode is not en abled by default. to allow 5 v toleranc e, the lvttl clamp diode needs to be enabled us ing settings in designer. hot-insertion and cold-sparing are not supported when the clamp diode is enabled. 2. can be implemented with an external resistor. 3. the oe input of the output buffer is automatically deasse rted by designer. 4. the oe input of the output buffer is automatically asserted by designer. figure 2-1 ? use of an external resistor for 5 v tolerance r ext . non-a c tel part a c tel fp g a 5 v 3.3 v 3.3 v p c i c lamp d io d e p c i c lamp d io d e
rtax-s/sl radtolerant fpgas 2-2 v5.4 operating conditions absolute maximum conditions stresses beyond those listed in table 2-2 may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. de vices should not be operated outside the recommended operating conditions in table 2-3 . overshoot/undershoot limits for ac signals, the input signal may undershoot during transitions to ?1.0 v for no longer than 10 % of the period or 11 ns (whichever is smaller). current during the transition must not exceed 95 ma. for ac signals, the input signal may overshoot during transitions to v cci + 1.0 v for no longer than 10 % of the period or 11 ns (whichever is smaller). current during the transition must not exceed 95 ma. note: the above specification does not apply to the pci standard. the rtax-s/sl pci i/os are compliant to the pci standard including the pci overshoot/undershoot specifications. table 2-2 ? absolute maxi mum ratings symbol parameter limits units t j junction temperature ?55 to +135 c v cca ac core supply voltage 1 ?0.3 to 1.8 v v cca dc core supply voltage ?0.3 to 1.7 v v cci dc i/o supply voltage ?0.3 to 3.75 v v ref dc i/o reference voltage ?0.3 to 3.75 v v i input voltage ?0.5 to 4.1 v v o output voltage ?0.5 to 3.75 v t stg storage temperature ?60 to +150 c v ccda 2 supply voltage for differential i/os ?0.3 to 3.75 v v pump supply voltage for external pump ?0.3 to 3.75 v notes: 1. the ac transient v cca limit is for radiation-induced transients less than 10 s duration and not intended for re petitive use. core voltage spikes from a single event transient will not negatively affect the reliability of the device if , for this non-repetitive event , the transient does not exceed 1.8 v at any time and the total time that th e transient exceeds 1.575 v does not exceed 10 s in duration. 2. v ccda must be greater than or equal to the highest v cci voltage table 2-3 ? rtax-s/sl recommended operating conditions parameter range military units junction temperature (t j ) ?55 to +125 c ambient temperature (t a ) 1 ?55 to +125 c 1.5 v core supply voltage 1.425 to 1.575 v 1.5 v i/o supply voltage 1.425 to 1.575 v 1.8 v i/o supply voltage 1.71 to 1.89 v 2.5 v i/o supply voltage 2.375 to 2.625 v 3.3 v i/o supply voltage 3.0 to 3.6 v 2.5 v v ccda i/o supply voltage (no differen tial i/o used) 2.375 to 2.625 v 3.3 v v ccda i/o supply voltage (differential or voltage-referenced i/o used) 2 3.0 to 3.6 v 3.3 v v pump supply voltage 3.0 to 3.6 v notes: 1. ambient temperature (t a ) is used for commercial and indus trial grades; case temperature (t c ) is used for military grades. 2. please see "vccda supply voltage" on page 2-11 more detail.
rtax-s/sl radtolerant fpgas v5.4 2-3 power-up/down sequence v cca , v cci , and v ccda can be powered up or powered down in any se quence. during power-up, all rtax-s/sl i/os are tristated until they reach the state defined by the design. calculating power dissipation table 2-4 ? rtax-s standby current device temperature i cca (ma) i cci (ma) i ccda (ma) i ccdiffa (ma) i ih , i il , i oz ( a) 1 rtax4000s typical 25oc 75 15 15 3.13 1 125oc 600 60 20 3.7 5 rtax2000s typical 25oc 50 10 7 3.13 1 125oc 500 35 10 3.7 5 rtax1000s typical 25oc 30 10 7 3.13 1 125oc 450 35 10 3.7 5 rtax250s typical 25oc 20 5 5 3.13 1 125oc 250 20 10 3.7 5 notes: 1. i ih , i il , or i oz values are measured with inputs at the same level as v cci for i ih and gnd for i il and i oz . 2. above values are maximum. 3. values in the i ccdiffa column refer to the current (in addition to i ccda ) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins. table 2-5 ? rtax-sl standby current device temperature i cca (ma) i cci (ma) i ccda (ma) i ccdiffa (ma) i ih , i il , i oz ( a) 1 rtax4000sl typical 25oc 40 15 15 3.13 1 125oc 300 60 20 3.7 5 rtax2000sl typical 25oc 30 10 7 3.13 1 125oc 150 35 10 3.7 5 rtax1000sl typical 25oc 20 10 7 3.13 1 125oc 90 35 10 3.7 5 rtax250sl typical 25oc 15 5 5 3.13 1 125oc 60 20 10 3.7 5 notes: 1. i ih , i il , or i oz values are measured with inputs at the same level as v cci for i ih and gnd for i il and i oz . 2. above values are maximum. 3. values in the i ccdiffa column refer to the cu rrent (in addition to i ccda ) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins.
rtax-s/sl radtolerant fpgas 2-4 v5.4 table 2-6 ? default c load / v cci c load (pf) v cci (v) p load (w/mhz) p 10 (w/mhz) p i/o (w/mhz)* single-ended without v ref lvcmos ? 15 (jesd8-11) 35 1.5 78.8 49.5 128.3 lvcmos ?18 35 1.8 113.4 73.4 186.8 lvcmos ? 25 35 2.5 218.8 148.0 366.8 lvttl 8 ma low slew 35 3.3 381.2 118.7 499.9 lvttl 12 ma low slew 35 3.3 381.2 138.6 519.8 lvttl 16 ma low slew 35 3.3 381.2 150.8 532.0 lvttl 24 ma low slew 35 3.3 381.2 169.2 550.4 lvttl 8 ma high slew 35 3.3 381.2 130.3 511.5 lvttl 12 ma high slew 35 3.3 381.2 165.9 547.1 lvttl 16 ma high slew 35 3.3 381.2 225.1 606.3 lvttl 24 ma high slew 35 3.3 381.2 267.5 648.7 pci 10 3.3 108.9 218.5 327.4 pci-x 10 3.3 108.9 162.9 271.8 single-ended with v ref sstl2-i 30 2.5 ? 171.2 171.2 sstl2-ii 30 2.5 ? 147.8 147.8 sstl3-i 30 3.3 ? 327.2 327.2 sstl3-ii 30 3.3 ? 288.4 288.4 hstl-i 20 1.5 ? 40.9 40.9 gtlp ? 33 10 3.3 ? 68.5 68.5 differential lvpecl ? 33 n/a 3.3 ? 260.6 260.6 lvds ? 25 n/a 2.5 ? 145.8 145.8 note: *p i/o = p 10 + c load * v cci 2 table 2-7 ? different components contributing to the to tal power consumption in rtax-s/sl devices symbol power component device-specific value (in w/mhz) rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl p1 core tile hclk power component 85.8 227.5 378.0 700 p2 r-cell power component 0.6 0.6 0.6 0.6 p3 hclk signal power dissipation 7.7 23.2 31.0 50 p4 core tile rclk power component 1.8 227.5 378.0 700 p5 r-cell power component 0.9 0.9 0.9 0.9 p6 rclk signal power dissipation 8.6 25.7 34.3 55 p7 power dissipation due to the switching activity on the r-cell 1.6 1.6 1.6 1.6 p8 power dissipation due to the switching activity on the c-cell 1.4 1.4 1.4 1.4 p9 power component associated with input voltage 10.0 10.0 10.0 10 p10 power component associated with output voltage see ta b l e 2 - 4 and table 2-5 on page 2-3 for per pin contribution. p11 power component asso ciated with the read operation in the ram block 25.0 25.0 25.0 25.0 p12 power component associated with the write operation in the ram block 30.0 30.0 30.0 30.0
rtax-s/sl radtolerant fpgas v5.4 2-5 p total = p dc + p ac p hclk = (p1 + p2 * s + p3 * sqrt[s]) * fs p clk = (p4 + p5 * s + p6 * sqrt[s]) * fs p r-cells = p7 * ms * fs p c-cells = p8 * mc * fs p inputs = p9 * pi * f pi p outputs = (p10 + c load * v cci 2 ) * po * f po p memory = p11 * n block * f rclk + p12 * n block * f wclk p dc =i cca * v cca + i cci * v cci + i ccda * v ccda + i ccdiffa * v ccda * n b_da_pairs p ac =p hclk + p clk + p r-cells + p c-cells + p inputs + p outputs + p memory n b_da_pairs = number of differential pairs or voltage referenced pins used s = number of r-cells clocked by this clock fs = clock frequency s = number of r-cells clocked by this clock fs = clock frequency ms = number of r-cells switching at each fs cycle fs = clock frequency mc = number of c-cells switching at each fs cycle fs = clock frequency pi = number of inputs f pi = average input frequency c load = output load (technology dependent) v cci = output voltage (technology dependent) po = number of outputs f po = average output frequency n block = number of ram/fifo blocks (1 block = 4k) f rclk = read-clock frequency of the memory f wclk = write-clock frequency of the memory
rtax-s/sl radtolerant fpgas 2-6 v5.4 power estimation example this example employs an rtax1000s/sl shift-register design with 1,080 r-cells, one c-ce ll, one reset input, and one output. this design also uses a single clock (hclk) at 100 mhz and is operat ed under room temperature. ms = 1,080 (in a shift register 100 % of r-cells are toggling at each clock cycle) fs = 100 mhz s = 1,080 => p hclk = (p1 + p2 * s + p3 * sqrt[s]) * fs = 163.8 mw and fs = 100 mhz => p r-cells = p7 * ms * fs = 172.8 mw mc = 1 (1 c-cell in this design) and fs = 100 mhz => p c-cells = p8 * mc * fs = 0.14 mw f pi ~ 0 mhz and pi= 1 (1 reset input => this is why f pi = 0) => p inputs = p9 * pi * f pi = 0 mw f po = 50 mhz c load = 35 pf v cci = 3.3 v and po = 1 => p outputs = (p10 + c load * v cci 2 ) * po * f po = 23.6 mw no ram/fifo in this shift-register => p memory = 0 mw p ac =p hclk + p clk + p r-cells + p c-cells + p inputs + p outputs + p memory = 360.4 mw p dc =i cca * v cca + i cci * v cci + i ccda * v ccda + i ccdiffa * v ccda * n b_da_pairs = 101.1 mw p total =p dc + p ac = 360.4 mw + 101.1 mw = 461.5 mw
rtax-s/sl radtolerant fpgas v5.4 2-7 thermal characteristics the temperature variable in actel designer software refers to the junction temperature, not the ambient, case or board temperature. this is an important distinction because dynamic and static power consumption causes the chip's junction temperature to be higher than the ambient, case or board temperature. eq 2-2 , eq 2-3 , and eq 2-4 show the relationship between thermal resistance, temperature, and power. eq 2-2 eq 2-3 eq 2-4 where: ja t j t a ? p ---------------- = jc t j t c ? p --------------- - = jb t j t b ? p ---------------- = ja = thermal resistance from junction to air jc = thermal resistance from junction to case jb = thermal resistance from junction to board t j = junction temperature t a = ambient temperature t c = case temperature t b = board temperature p = power table 2-8 ? package thermal characteristics product package type ja jc jb units rtax250s/sl cq208 19.9 0.8 n/a c/w cq352 16.8 0.7 n/a c/w cg624 13.7 tbd tbd c/w rtax1000s/sl cq352 13.3 0.4 n/a c/w cg624 10.8 5.6 4.5 c/w rtax2000s/sl cq256 15.8 0.25 n/a c/w cq352 12.3 0.2 n/a c/w cg624 9.7 4.3 3.5 c/w cg1152 9.0 2.0 2.6 c/w rtax4000s/sl cq352 12.3 0.2 n/a c/w cg1272 8.0 2.0 2.2 c/w notes: 1. ja are estimated at still air. 2. jc for cqfp refers to the thermal resistance between the junction and the botto m surface of the package. 3. jc for cg packages refers to the thermal resistance be tween the junction and the top surface of the package. 4. the jb values in the table are simulated under conduction heat transfer only.
rtax-s/sl radtolerant fpgas 2-8 v5.4 calculation for power sample case 1: convection 0 a sample calculation of the power diss ipation allowed for an rt ax1000s/sl-cg624 in still air is shown below. assume that the maximum junction temperatur e is maintained at 110c and the ambi ent temperature is 50c. the maximum power allowed can be estimated using the equation below. t j = 110c t a = 50c p = 5.55 w sample case 2: convection = 0 a sample calculation of the power diss ipation when there is no air in the en vironment is shown below. an rtax1000s/ sl-cq352 is attached to the board with a thermal adhesive between the package body. the thermal resistance of the paste is 0.58c/w. since air is not pres ent in the environment, most of the he at will be flowing through th e bottom of the package, through the thermal paste, and to the board . neglecting the heat flowi ng through the package leads, the maximum power allowed can be estimated as shown in the equations below. t j = 110c cb = thermal resistance of the thermal past e from case to board (i.e., = 0.58c/w) t b = 70c p = 40.8 w the thermal resistances, shown in table 2-8 on page 2-7 , are based on the simulations done with test conditions and test boards configurations specified in jedec specification jesd51. = figure 2-2 ? heat flow when air is present ja 10.8c/w 110c 50c ? p ----------------------------------- == solder columns air pcb jb (total) 110c 70c ? p ----------------------------------- = jb (total) jc cb + = jc cb + 110c 70c ? p ----------------------------------- = 0.4c/w 0.58c/w + 110c 70c ? p ---------------------------------- - = figure 2-3 ? heat flow in a vacuum thermal adhesive pcb
rtax-s/sl radtolerant fpgas v5.4 2-9 timing characteristics rtax-s/sl devices are manufactured in a cmos process, therefore, device perfor mance varies according to temperature, voltage, and process variations. minimum timing parameters reflect maximum operating voltage, minimum operating temperatur e, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temper ature, and worst-case processing . the derating factors shown in table 2-9 should be applied to all timing data contained within this datasheet. all timing numbers listed in this datasheet represent sample timing characteristics of rtax-s/sl devices. actual timing delay values are design-specific and can be derived from the timer tool in actel?s designer software after place-and- route. table 2-9 ? temperature and voltage ti ming derating factors (normalized to worst-case military, t j = 125c, v cca = 1.4 v) v cca junction temperature ?55c ?40c 0c 25c 70c 85c 125c 1.4v 0.74 0.75 0.80 0.84 0.89 0.92 1.00 1.425v 0.72 0.74 0.79 0.82 0.88 0.91 0.98 1.5v 0.69 0.71 0.75 0.78 0.84 0.86 0.94 1.575v 0.66 0.68 0.72 0.75 0.80 0.83 0.90 1.6v 0.65 0.67 0.71 0.74 0.79 0.82 0.89 notes: 1. the user can set the junction temperature in designer software to be any integer value in the range of ?55 c to 125 c. 2. the user can set the core voltage in designer software to be any value between 1.4v and 1.6v.
rtax-s/sl radtolerant fpgas 2-10 v5.4 timing model hardwired clock 1 routed clock 1 note: timing data is for the rtax2000s/sl, ?1 speed. figure 2-4 ? timing model c om b inatorial c ell c om b inatorial c ell c om b inatorial c ell c om b inatorial c ell dq dq dq y f c o + + route d c lo c k re g ister c ell lvpe c l lvpe c l lvd s re g ister c ell har d wire d or route d c lo c k route d or har d wire d i/o mo d ule i/o mo d ule (re g istere d ) i/o mo d ule (nonre g istere d ) i/o mo d ule (non- re g istere d ) i/o mo d ule (nonre g istere d ) y buffer mo d ule buffer mo d ule buffer mo d ule c arry c hain i/o i/o lvttl output drive s tren g th = 4 (24ma) hi g h s lew rate t h c kh = 3. 6 5 ns f max (external) = 350 mhz f max (internal) = 700 mhz t s ud = 0.31 ns t i c lkq = 0.91 ns t dp = 1.83 ns t rd2 = 0.84 ns t dp = 2.00 ns t h c kl = 3.48 ns t r c kl = 3.55 ns t r c o = 0.9 6 ns t s ud = 0.21 ns t rd1 = 0. 66 ns t pd = 0.95 ns t r c kl = 3.54 ns f max (external) = 350 mhz f max (internal) = 700 mhz t r c o = 0.9 6 ns t s ud = 0.21 ns t bpfd = 0.21ns t py = 1.2 6 ns g tl + 3.3v t o c lkq = 0.91 ns t s ud = 0.31 ns t bfpd = 0.17 ns t pd = 0.95 ns t bfpd = 0.17 ns t pd c = 0.70 ns t cc y = 0.7 6 ns t py = 3.51 ns t py = 2.45 ns t rd1 = 0. 66 ns t rd2 = 0.84 ns t rd3 = 1.07 ns t r c kh = 3.71 ns t r c kl = 3.54 ns lvttl t dp = 1.85 ns lvttl t dp = 1.85 ns lvttl t dp = 1.85 ns external setup =(t dp + t rd2 + t sud ) ? t hckh = (1.85 + 0.84 + 0.31) ? 3.65 = ?0.61 clock-to-out (pad-to-pad) =t hckh + t rco + t rd1 + t py = 3.65 + 0.96 + 0.66 + 3.51 = 8.78 ns 1. calculations are examples of how to calculate related parame ters and do not necessary matc h the path represented in the "timing model" . external setup =(t dp + t rd2 + t sud ) ? t rckh = (1.85 + 0.84 + 0.31) ? 3.54 = ?0.71 ns clock-to-out (pad-to-pad) =t rckh + t rco + t rd1 + t py = 3.71 + 0.96 + 0.66 + 3.51 = 8.84 ns
rtax-s/sl radtolerant fpgas v5.4 2-11 i/o specifications pin descriptions supply pins gnd ground low supply voltage. v cca supply voltage supply voltage for array (1.5 v). v ccibx supply voltage supply voltage for i/os. bx is the i/o bank id ? 0 to 7. see "user i/os" on page 2-12 for more information. unused v cci bx i/o banks may be tied to gnd or can be tied to other used v cci bx i/o banks within the same device. v ccda supply voltage supply voltage for the i/o diff erential amplifier and jtag and probe interfaces. v ccda is either 3.3 v or 2.5 v and must use 3.3 v when voltage-referenced and/or differential is used. additionally, v ccda must be greater than or equal to any v cci voltages (i.e. v ccda v cci bx). v pump supply voltage (external pump) in low-power mode, v pump will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). the device starts using the external charge pump when the voltage level on v pump reaches 3.3 v. 2 in normal device operation, when using the internal charge pump, v pump can be directly tied or through a 1k resistor to gnd. user-defined supply pins v ref supply voltage reference voltage for i/o banks. v ref pins are configured by the user from regular i/o pins; v ref are not in fixed locations. there can be one or more v ref pins in an i/o bank. global pins hclka/b/c/d dedicated (hardwired) clocks a, b, c, and d these pins are the clock in put for sequential modules. input levels are compatib le with all supported i/o standards (there is a p/n pin pair for support of differential i/o standards). this input is directly wired to each r-cell and offers clock speeds independent of the number of r-cells being driven. hclk pins may be used either as hclk inputs or as user i/os. if they are not being used for either purpose, acte l recommends that they are tied to ground. clke/f/g/h global clocks e, f, g, and h these pins are clock inpu ts for clock distribution networks. input levels are co mpatible with all supported i/o standards (there is a p/n pin pair for support of differential i/o standards). the clock input is buffered prior to clocking the r-cells. clk pins may be used either as clk inputs or as user i/os . if they are not being used for either purpose, actel recommends that they are tied to a known state. 2. when v pump = 3.3v, it shuts off the internal charge pump.
rtax-s/sl radtolerant fpgas 2-12 v5.4 jtag/probe pins pra/b/c/d 3 probes a, b, c, and d the dedicated probe pins are used to output data from any user-defined design node within the device (controlled with silicon ex plorer ii). these independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. the pins? probe capabilities can be permanently disabled to protect programmed design confidentiality. refer to table 2-102 on page 2-100 for recommendations on pin status for flight boards. tck 2 test c lo ck test clock input for jtag boundary-scan testing and diagnostic probe (s ilicon explorer ii). tdi 2 test data input serial input for jtag boundary-scan testing and diagnostic probe. tdi is equi pped with an internal pull- up resistor with approximately 10 k resistance. tdo 2 test data output serial output for jtag boundary-scan testing. tms test mode select the tms pin controls the use of the ieee 1149.1 boundary-scan pins (tck, tdi, tdo, trst). tms is equipped with an internal pull-up resistor with approximately 10 k resistance. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. the trst pin is equipped with a programmable pull-up resistor with approximately 10 k resistance (i.e. with or without the pull-up resistor). this pin must be hardwired to ground for flight. special functions nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. user i/os 4 introduction the rtax-s/sl family featur es a flexible i/o structure, supporting a range of mixed voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) with its bank-selectable i/os. table 2-10 on page 2-13 contains the i/o standa rds supported by the rtax-s/sl family. unused i/os are conf igured as follows: ? output buffer is disabled (with tristated value of hi-z) ? input buffer is disabled (w ith tristated value of hi-z) ? no pull-up/pull-down is programmed in actel designer software, unused rtax-s/sl i/os are configured as tristate with no pull-up resistors. each i/o provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. all i/o standards are 3.3 v tolerant, and i/o standards, except 3.3 v pci, are capable of hot insertion and cold sparing. 3.3 v pci is also 5 v tolerant with the aid of an external resistor (see "5 v tolerance" on page 2-1 ). each i/o includes three regist ers: an input (inreg), an output (outreg), and an enable register (enreg). by design, all user flip-flops in the rtax-s/sl fpgas are immune to seus including the following three registers located in every i/o cell buffer: inreg, outreg, and enreg. i/os are organized into banks, and there are eight banks per device ? two per side ( figure 2-7 on page 2-21 ). each i/o bank has a common v cci , the supply voltage for its i/os. 3. actel recommends that you use a series termination resistor on every probe connector (tdi, tc k, tdo, pra, prb, prc, and prd). the series termination is used to prev ent data transmission corruption (i.e., du e to reflection from the fpga to the prob e connector) during probing and reading back the checksum. with an internal setup we have seen 70-ohm termination resistor improved the signal transmission. since the series termination depends on the setup, actel recommends users to calculate the termination resistor for their own setup. below is a guideline on how to calcul ate the resistor value. the resistor value should be chosen so th at the sum of it and the probe signal?s driver impedance equals the effective trace impedance. z0 = rs + zd z0 = trace impedance (silicon explorer?s breakout cable?s resi stance + pcb trace impedance ), rs = series termination, zd = probe signal?s driver impedance. the termination resistor should be placed as close as possible to the driver. among the probe signals, tdi, tck, and tm s are driven by silicon explorer. a54sx16 is used in silicon explorer and hence the driver impedances needs to be calculated from rtax-s ibis models (mixed voltage operation). pr a, prb, prc, prd, and tdo are driven by the fpga and driver impe dance can also be calculated from the ibis model . silicon explorer?s breakout cable?s re sistance is usually close to 1 ohm. 4. do not use an external resistor to pull the i/o above v cci for a higher logic ?1? voltage le vel. the desired higher logic ?1? voltage level will be degraded due to a small i/o cu rrent, which exists when the i/o is pulled up above v cci .
rtax-s/sl radtolerant fpgas v5.4 2-13 for voltage-referenced i/os, each bank also has a common reference-voltage bus, v ref . while v ref must have a common voltage for an entire i/o bank, its location is user-selectable. in other words, any user i/o in the bank can be selected to be a v ref . the location of the v ref pin should be selected according to the following rules: ? any pin that is assigned as a v ref can control a maximum of eight user i/o pad locations in each direction (16 total maximum) within the same i/o bank. ? i/o package locations listed as no-connects are counted as part of the 16 maximum. in many cases, this leads to fewer than eight user i/o package pins in each direction being controlled by a v ref pin. ? dedicated i/o pins (gnd, v cci ...) are not counted as part of the 16. ? the user i/o pad immedi ately adjacent on either side of the v ref pin may only be used as an input. the exception is when there is a v cci /gnd pair separating the v ref pin and the user i/o pad location. the differential amplifier supply voltage v ccda should be connected to 3.3 v. when neither voltage-referenced nor differential i/os are used, v ccda may be connected to 2.5 v when v cci <= 2.5 v in a given i/o bank; however, it is still recommended to connect v ccda to 3.3 v. the user can gain access to the various i/o standards in three ways: ? instantiate specific libra ry macros that represent the desired specific standard ? use generic i/o macros and then use actel designer?s pineditor to specify the desired i/o standards. (please note that this is not applicable to differential standards.) ? a combination of the first two methods please refer to the i/o features in axcelerator family devices application note and the antifuse macro library guide for more details. table 2-10 ? i/o standards supported by the rtax-s/sl family i/o standard input/output supply voltage (v cci ) input reference voltage (v ref ) board termination voltage (v tt ) lvttl 3.3 n/a n/a lvcmos 2.5 v 2.5 n/a n/a lvcmos 1.8 v 1.8 n/a n/a lvcmos 1.5 v (jdec8-11) 1.5 n/a n/a 3.3 v pci 3.3 n/a n/a gtl+ 3.3 v 3.3 1.0 1.2 gtl+ 2.5 v * 2.5 1.0 1.2 hstl class 1 1.5 0.75 0.75 sstl3 class 1 and ii 3.3 1.5 1.5 sstl2 class1 and ii 2.5 1.25 1.25 lvds 2.5 n/a n/a lvpecl 3.3 n/a n/a note: * 2.5 v gtl+ is not supported across the full military temperature range.
rtax-s/sl radtolerant fpgas 2-14 v5.4 simultaneous switching outputs (sso) actel defines ssos as any outputs that transition in phase within a 1 ns window. the m easurements made by actel are based on the following worst-case conditions: 1. the switching outputs ar e adjacent to the quiet output on either side. 2. all unused i/o buffers are tristated so they do not help either ground or v cc . 3. a worst-case package was used. when multiple output drive rs switch simultaneously, they induce a voltage drop in the chip/package power distribution. this simultan eous switching momentarily raises the ground voltage within the device relative to the system ground. this apparent shift in the ground potential to a non-zero valu e is known as simultaneous switching noise (ssn) or more commonly, ground bounce. ssn becomes more of an issue in high pin count packages and when using high performance devices such as the rtax-s/sl family. please refer to the simultaneous switching noise and signal integrity application note fo r more information. i/o banks and compatibility since each i/o bank has its own user-assigned input reference voltage (v ref ) and an input/output supply voltage (v cci ), only i/os with comp atible standards can be assigned to the same bank. table 2-11 shows the compatible i/o standards for a common v ref (for voltage-referenced standards). similarly, table 2-12 shows compatible standards for a common v cci . table 2-13 on page 2-15 summarizes the different combinations of voltages and i/o standards that can be used together in the same i/o bank. note that two i/o standards are compatible if: ? their v cci values are identical ? their v ref standards are identical (if applicable) for example, if lvttl 3.3 v (v ref = 1.0v) is used, then the other available (i.e. compatible) i/o standards in the same bank are lvttl 3.3 v pci, gtl+, and lvpecl. also note that when mu ltiple i/o standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all i/o standards used in the bank. for instance, when using lvcmos2.5 (+/-8 % v cci tolerance) and lvds (+/-5 % v cci tolerance) within an i/o bank, the maximum voltage tolerance of the bank will be +/-5 % v cci . table 2-11 ? compatible i/o standards for different v ref values v ref compatible standards 1.5 v sstl 3 (class i and ii) 1.25 v sstl 2 (class i and ii) 1.0 v gtl+ (2.5 v and 3.3 v outputs) 0.75 v hstl (class i) table 2-12 ? compatible i/o standards for different v cci values v cci 1 compatible standards v ref 3.3 v lvttl, pci, lvpecl, gtl+ 3.3v 1.0 3.3 v sstl 3 (class i and ii), lvttl, pci, lvpecl 1.5 2.5 v lvcmos 2.5v, gtl+ 2.5v, lvds 2 1.0 2.5 v lvcmos 2.5v, sstl 2 (classes i and ii), lvds 2 1.25 1.8 v lvcmos 1.8v n/a 1.5 v lvcmos 1.5v, hstl class i 0.75 notes: 1. v cci is used for both inputs and outputs. 2. v cci tolerance is 5%.
rtax-s/sl radtolerant fpgas v5.4 2-15 table 2-13 ? legal i/o usage matrix i/o standard lvttl 3.3 v lvcmos 2.5 v lvcmos1.8 v lvcmos1.5 v (jesd8-11) 3.3 v pci gtl + (3.3 v) gtl + (2.5 v) hstl class i (1.5 v) sstl2 class i & ii (2.5 v) sstl3 class i & ii (3.3 v) lvds (2.5 v 5%) lvpecl (3.3 v) lvttl 3. 3v (v ref =1.0v) ? ??? ?? ? ? ??? ? lvttl 3. 3v(v ref =1.5v) ? ??? ? ???? ? ? ? lvcmos 2.5 v (v ref =1.0v) ? ? ???? ? ??? ? ? lvcmos 2.5 v (v ref =1.25v) ? ? ?????? ? ? ? ? lvcmos1.8 v ? ? ? ????????? lvcmos1.5 v (v ref =1.75 v) (jesd8-11) ? ? ? ? ??? ? ??? ? 3.3 v pci (v ref =1.0v) ? ??? ?? ? ? ??? ? 3.3 v pci (v ref =1.5v) ? ??? ? ???? ? ? ? gtl+ (3.3 v) ? ??? ?? ? ? ??? ? gtl+ (2.5 v) ? ? ???? ? ? ??? ? hstl class i ? ? ? ? ??? ? ??? ? sstl2 class i & ii ? ? ?????? ? ? ? ? sstl3 class i & ii ? ??? ? ???? ? ? ? lvds (v ref =1.0 v) ? ? ???? ? ??? ? ? lvds (v ref =1.25 v) ? ? ?????? ? ? ? ? lvpecl (v ref =1.0 v) ? ??? ?? ? ? ??? ? lvpecl (v ref =1.5 v) ? ??? ? ???? ? ? ? notes: 1. note that gtl+2.5 v is not supported ac ross the full military temperature range. 2. a " ? " indicates whether standards can be used within a bank at the same time. examples: a) lvttl can be used with 3.3 v pci and gtl+ (3.3 v), when v ref = 1.0 v (gtl+ requirement). b) lvttl can be used with 3.3 v pci and sstl3 class i and ii, when v ref = 1.5 v (sstl3 requirement). c) lvds v cci = 2.5 v 5%.
rtax-s/sl radtolerant fpgas 2-16 v5.4 i/o clusters each i/o cluster incorporates two i/o module s, four rx modules and two tx modules, and a buffer module. in turn, each i/o module contains one inpu t register (inreg), one output register (o utreg), and one enable register (enreg) ( figure 2-5 ). using an i/o register to access the i/o registers, re gisters must be instantiated in the netlist and then co nnected to the i/os. usage of each i/o register (register co mbining) is individually controlled and can be sele cted/deselected using the pineditor tool in actel's designer software. i/o register combining can also be cont rolled at the device level, affecting all i/os. please note, the i/o register option is deselected by default in any given design. 5 in addition, designer software provides a global option to enable/disable the usage of regi sters in the i/os. this option is design specific. the sett ing for each individual i/o overrides this global option. furthermore, the global set fuse option in the design er software, when checked, causes all i/o registers to output logic high at device power-up. using the weak pull-up and pull-down circuits each rtax-s/sl i/o comes with a weak pull-up/down circuit (on the order of 10 k ). i/o macros are provided for combinations of pull up/down for lvttl, lvcmos (2.5 v, 1.8 v, and 1.5 v) stan dards. these macros can be instantiated if a keeper ci rcuit for any input buffer is required. figure 2-5 ? i/o cluster interface enreg din yout y dcin outreg din yout inreg i/o cluster fpga logic core oep uop uip slew rate i/o oen uon uin drive strength slew rate drive strength p pad n pad routed input track routed input track output track routed input track routed input track output track output track enreg din yout y dcin outreg din yout inreg i/o v ref v ref bsr bsr routed input track routed input track output track routed input track routed input track 5. please note that register combining for multi fanout nets is not supported.
rtax-s/sl radtolerant fpgas v5.4 2-17 customizing the i/o ? a five-bit programmabl e input delay element is associated with each i/o. the value of this delay is set on a bank-wide basis ( table 2-14 ). it is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the i/ o). when the input buffer drives a register within the i/o, the delay element is activated by default to ensure a zero hold-time. the default setting for this property can be set in designer. when the input buffer does not drive a register, the delay element is deactivated to provide higher performance. again, this can be ov erridden by changing the default setting for this property in designer. ? the slew-rate value for the lvttl output buffer can be programmed and can be set to either slow or fast. ? the drive strength value for lvttl output buffers can be programmed as well. there are four different drive strength values ? 8ma, 12ma, 16ma, or 24ma ? that can be specified in designer. 6 using the differential i/o standards differential i/o macros should be instantiated in the netlist. the settings for these i/o standards cannot be changed inside designer. note that there are no tristated or bidirectional i/o buffers for differential standards. using the voltage-referenced i/o standards using these i/o standards is similar to that of single- ended i/o standards. their settings can be changed in designer. using ddr (double data rate) in double data rate mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidth and signa l integrity requirements, making it very efficient for implementing very high- speed systems. to implement a ddr, user s must do the following: 1. instantiate an input buff er (with the required i/o standard). 2. instantiate the ddr_reg macro ( figure 2-6 ). 3. connect the output from the input buffer to the input of the ddr macro. 4. ddr supports all i/o standards. 5. the ddr macro in smar tgen can be used to implement ddr. 6. bit width and i/o standard can be chosen in smartgen. macros for specific i/o standards there are different macro ty pes for any i/o standard or feature that determine the required v cci and v ref voltages for an i/o. the gene ric buffer macros require the lvttl standard with slow slew rate and 24 ma-drive table 2-14 ? bank wide delay values ?1 std. bit setting delay (ns) 0 0.88 1.03 1 1.10 1.29 2 1.21 1.42 3 1.44 1.69 4 1.53 1.80 5 1.75 2.06 6 1.86 2.19 7 2.09 2.46 8 2.16 2.54 9 2.38 2.80 10 2.49 2.93 11 2.72 3.20 12 2.81 3.30 13 3.04 3.57 14 3.15 3.70 15 3.37 3.96 16 3.39 3.98 17 3.61 4.25 18 3.72 4.38 19 3.95 4.64 20 4.04 4.75 21 4.27 5.01 6. these values are minimum drive strengths. 22 4.38 5.14 23 4.60 5.41 24 4.67 5.49 25 4.90 5.76 26 5.01 5.89 27 5.23 6.15 28 5.32 6.26 29 5.55 6.52 30 5.66 6.65 31 5.88 6.92 note: data for rtax2000s/sl is shown in the table above; it was measured at v cca = 1.425 and 125c. table 2-14 ? bank wide delay values ?1 std. bit setting delay (ns)
rtax-s/sl radtolerant fpgas 2-18 v5.4 strength. lvttl can support high slew rate but this should only be used for critical signals. most of the macro symbols represent variations of the six generic symbol types: ? clkbuf: clock buffer ? hclkbuf: hardwired clock buffer ? inbuf: input buffer ? outbuf: output buffer ? tribuff: tristate buffer ? bibuf: bidirectional buffer other macros include the following: ? differential i/o standard macros: the lvds and lvpecl macros either have a pair of differential inputs (e.g. inbuf_lvds) or a pair of differential outputs (e.g. outbuf_lvpecl). ? pull-up and pull-down va riations of the inbuf, bibuf, and tribuff macros. these are available only with ttl and lvcmos thresholds. they can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. this allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. ? ddr_reg macro. it can be connected to any i/o standard input buffers (i.e ., inbuf) to implement a double data rate register. designer software will map it to the i/o module in the same way it maps the other registers to the i/o module. figure 2-6 ? ddr register dqr qf e c lr pre c lk
rtax-s/sl radtolerant fpgas v5.4 2-19 table 2-15 , table 2-16 , and table 2-17 on page 2-20 list all the available macro name s differentiated by i/o standard, type, slew rate, and drive strength. table 2-15 ? macros for single-e nded i/o standards standard v cci macro names lvttl 3.3 v clkbuf, hclkbuf inbuf, outbuf, outbuf_s_8, outbuf_s_12, outbuf_s_16, outbuf_s_24, outbuf_f_8, outbuf_f_12, outbuf_f_16, outbuf_f_24, tribuff, tribuff_s_8, trib uff_s_12, tribuff _s_16, tribuff_s_24, tribuff_f_8, tribuff_f_12, tribuff_f_16, tribuff_f_24, bibuf, bibuf_s_8, bibuf_s_12, bibuf_s_16, bibuf_s_24, bibuf_f_8, bibuf_f_12, bibuf_f_16, bibuf_f_24, 3.3v pci 3.3 v clkbuf_pci, hclkbuf_pci, inbuf_pci, outbuf_pci, tribuff_pci, bibuf_pci lvcmos25 2.5 v clkbuf_lvcmos25, hclkbuf_lvcmos25, inbuf_lvcmos25, outbuf_lvcmos25, tribuff_lvcmos25, bibuf_lvcmos25 lvcmos18 1.8 v clkbuf_lvcmos18, hclkbuf_lvcmos18, inbuf_lvcmos18, outbuf_lvcmos18, tribuff_lvcmos18, bibuf_lvcmos18 lvcmos15 (jesd8-11) 1.5 v clkbuf_lvcmos15, hclkbuf_lvcmos15, inbuf_lvcmos15, outbuf_lvcmos15, tribuff_lvcmos15, bibuf_lvcmos15
rtax-s/sl radtolerant fpgas 2-20 v5.4 table 2-16 ? i/o macros for differential i/o standards standard v cci macro names lvpecl 3.3 v clkbuf_lvpecl, hclkbuf_lvpecl, inbuf_lvpecl, outbuf_lvpecl lvds 2.5 v clkbuf_lvds, hclkbuf_lvds, inbuf_lvds, outbuf_lvds table 2-17 ? i/o macros for voltage-referenced i/o standards standard v cci v ref macro names gtl+ 3.3 v 1.0 v clkbuf_gtp33, hclkbuf_gtp 33, inbuf_gtp33, outbuf _gtp33, tribuff_gtp33, bibuf_gtp33 gtl+ 2.5 v 1.0 v clkbuf_gtp25, hclkbuf_gtp 25, inbuf_gtp25, outbuf _gtp25, tribuff_gtp25, bibuf_gtp25 sstl2 class i 2.5 v 1.25 v clkbuf_sstl2_i, hclkb uf_sstl2_i, tribuff_sstl2_i, bibuf_sstl2_i, inbuf_sstl2_i, outbuf_sstl2_i sstl2 class ii 2.5 v 1.25 v clkbuf_sstl2_ii, hclkbuf_s stl2_ii, tribuff_sstl2_ii, bi buf_sstl2_ii, inbuf_sstl2_ii, outbuf_sstl2_ii sstl3 class i 3.3 v 1.5 v clkbuf_sstl3_i, hclkbuf _sstl3_i, tribuff_sstl3_i, bi buf_sstl3_i, inbuf_sstl3_i, outbuf_sstl3_i sstl3 class ii 3.3 v 1.5 v clkbuf _sstl3_ii, hclkbuf_sstl3_ii, tribuff_s stl3_ii, bibuf_sstl3_ii, inbuf_sstl3_ii, outbuf_sstl3_ii hstl class i 1.5 v 0.75 v cl kbuf_hstl_i, bibuf_hstl_i, hclkbuf_h stl_i, inbuf_hstl_i, outbuf_hstl_i, tribuff_hstl_i
rtax-s/sl radtolerant fpgas v5.4 2-21 user i/o naming conventions due to the complex and flexible nature of the rtax-s/sl fam ily?s user i/os, a naming scheme is used to show the details of the i/o. the naming scheme explains to which bank an i/o belongs, as well as the pairing and pin polarity for differential i/os ( figure 2-7 ). figure 2-7 ? i/o bank and dedicated pin layout figure 2-8 ? general naming schemes pr c prd prb pra tdo tdi t c k tm s tr s t c orner4 c orner3 c orner1 i/o bank 3 i/o bank 2 i/o bank 0 i/o bank 5 i/o bank 1 i/o bank 4 i/o bank 7 i/o bank 6 c orner2 rtax- s / s l g nd v cc da g nd v cc da v pump g nd v cc da g nd v cc da g nd v cc da g nd v cc da g nd v cc da g nd v cc da g nd v cc a g nd v cc a g nd v cc a g nd v cc a g nd v cc a g nd v cc a g nd v cc i 2 g nd v cc i 1 g nd g nd v cc i 5 g nd v cc i 4 g nd v cc da g nd v cc da g nd v cc da g nd v cc a g nd v cc a g nd v cc i 6 g nd v cc i 7 g nd v cc i 3 v cc i 0 ioxxxbxfx fx refers to an unimplemented feature and can be ignored bank i/d 0 through 7, clockwise from iob nw p - positive pin/ n- negative pin pair number in the bank, starting at 00, clockwise from iob nw io12pb1f1 is the positive pin of the thirteenth pair of the first i/o bank (iob ne). io12pb1 combined with io12nb1 form a differential pair. for those i/os that can be employed either as a user i/o or as a special function, the following nomenclature is used: ioxxxbxfx/special_function_name ioxxpb1fx/clkx this pin can be configured as a clock input or as a user i/o examples:
rtax-s/sl radtolerant fpgas 2-22 v5.4 i/o standard electrical specifications table 2-18 ? input capacitance symbol parameter conditions min. max. units c in input capacitance v in = 0, f =1.0 mhz 10 pf c inclk input capacitance on clock pin v in = 0, f =1.0 mhz 10 pf table 2-19 ? i/o weak pull-up/pull-down resistances 1 minimum and maximum weak pull-up/pull-down resistance values r(pull up) (k ) 2 r(pull down) (k ) 3 i/o configuration (v cci ) min. max. min. max. 3.3 v 35 65 30 60 2.5 v 50 75 40 85 1.8 v 80 140 70 130 1.5 v 100 210 90 180 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and proces s. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/downl oad/ibis/default.aspx . 2. r (pull-down-max) = ( v olspec) / i olspec 3. r (pull-up-max) = ( v ccimax ? v ohspec) / i ohspec table 2-20 ? i/o input rise time and fall time* input buffer input rise/fall time (min) input rise/fall time (max) lvttl no requirement 50 ns lvcmos 2.5 v no requirement 50 ns lvcmos 1.8 v no requirement 50 ns lvcmos 1.5 v no requirement 50 ns pci no requirement 50 ns pcix no requirement 50 ns gtl+ no requirement 50 ns hstl no requirement 50 ns sstl2 no requirement 50 ns hstl3 no requirement 50 ns lvds no requirement 50 ns lvpecl no requirement 50 ns note: *input rise/fall time applies to all inputs, including clock or data. inputs have to ramp up/do wn linearly, in a monotonic way. glitches or a plateau may cause double-clocking. they mu st be avoided. for output rise/fall time, refer to ibis models for extraction.
rtax-s/sl radtolerant fpgas v5.4 2-23 figure 2-9 ? input buffer delays figure 2-10 ? output buffer delays y in inbuf pad ln y gnd input high 0v v cca t dp t dp v trip v trip 50 % 50 % (rising) (falling) ln ln out gnd 50 % 50 % tribuf en en out gnd 50 % 10 % 50 % en out gnd 50 % 50 % 90 % to ac test loads (shown below) out pad v tt t enhz t enhz v oh v trip gnd/v tt v tt v ol t enlz t enlz v cci /v tt v trip v trip v trip v oh t py t py (t dlh ) (t dhl ) v cca v cca v cca v ol
rtax-s/sl radtolerant fpgas 2-24 v5.4 i/o module timing characteristics figure 2-11 ? timing model figure 2-12 ? input register timing characteristics oe out in d q c lk outre g enre g inre g d q q q d d c lk (route d or har d wire d ) e d q c lr pre s et c lk t s ue t he t s ud t hd t i c lkq t wa s yn t ha s yn t c lr t rea s yn t c pwhl t c pwlh t pre s et t wa s yn t ha s yn t rea s yn
rtax-s/sl radtolerant fpgas v5.4 2-25 figure 2-13 ? output register timing characteristics figure 2-14 ? output enable register timing characteristics e d q c lr pre s et c lk t s ue t he t s ud t hd t o c lkq t wa s yn t ha s yn t c lr t rea s yn t c pwhl t c pwlh t pre s et t wa s yn t ha s yn t rea s yn e d q c lr pre s et c lk t s ue t he t s ud t hd t o c lkq t wa s yn t ha s yn t c lr t rea s yn t c pwhl t c pwlh t pre s et t wa s yn t ha s yn t rea s yn
rtax-s/sl radtolerant fpgas 2-26 v5.4 3.3 v lvttl low-voltage transistor-transistor logic is a general purpose st andard (eia/jesd) for 3.3 v ap plications. it uses an lvttl input buffer and push-pull output buffer. ac loadings table 2-21 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 0.8 2.0 3.6 0.4* 2.4 24 ?24 note: for rtax250s/sl-cq352 devices only, v ol limits are 500 mv across all operating temperatures. figure 2-15 ? ac test loads table 2-22 ? ac waveforms, measuring po ints, and capacitive load input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) 0 3.0 1.40 n/a 35 * measuring point = v trip r to v cc i for t plz /t pzl r to g nd for t phz /t pzh 35 pf for t pzh /t pzl 5 pf for t phz /t plz test point test point 35 pf for tristate r=1 k for t p d
rtax-s/sl radtolerant fpgas v5.4 2-27 timing characteristics table 2-23 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. lvttl i/o module drive strength = 1 (8 ma) / low slew rate t dp input buffer 1.85 2.17 ns t py output buffer 15.82 18.60 ns t enzl enable to pad delay through the output buffer?high to z 16.64 19.56 ns t enzh enable to pad delay through the output buffer?z to high 15.56 18.29 ns t enlz enable to pad delay through the output buffer?low to z 1.63 1.64 ns t enhz enable to pad delay through the output buffer?z to low 1.97 1.97 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 2 (12 ma) / low slew rate t dp input buffer 1.85 2.17 ns t py output buffer 13.26 15.58 ns t enzl enable to pad delay through the output buffer?high to z 13.56 15.94 ns t enzh enable to pad delay through the output buffer?z to high 13.28 15.61 ns t enlz enable to pad delay through the output buffer?low to z 1.81 1.82 ns t enhz enable to pad delay through the output buffer?z to low 2.24 2.24 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns
rtax-s/sl radtolerant fpgas 2-28 v5.4 t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 3 (16 ma) / low slew rate t dp input buffer 1.85 2.17 ns t py output buffer 12.04 14.16 ns t enzl enable to pad delay through the output buffer?high to z 12.46 14.65 ns t enzh enable to pad delay through the output buffer?z to high 12.05 14.17 ns t enlz enable to pad delay through the output buffer?low to z 1.95 1.96 ns t enhz enable to pad delay through the output buffer?z to low 2.52 2.53 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 4 (24 ma) / low slew rate t dp input buffer 1.85 2.17 ns t py output buffer 11.41 13.41 ns t enzl enable to pad delay through the output buffer?high to z 11.58 13.61 ns t enzh enable to pad delay through the output buffer?z to high 11.43 13.43 ns t enlz enable to pad delay through the output buffer?low to z 2.01 2.02 ns t enhz enable to pad delay through the output buffer?z to low 2.59 2.60 ns table 2-23 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-29 t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 1 (8 ma) / high slew rate t dp input buffer 1.85 2.17 ns t py output buffer 4.78 5.62 ns t enzl enable to pad delay through the output buffer?high to z 5.06 5.95 ns t enzh enable to pad delay through the output buffer?z to high 4.61 5.42 ns t enlz enable to pad delay through the output buffer?low to z 1.98 1.99 ns t enhz enable to pad delay through the output buffer?z to low 2.03 2.03 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-23 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-30 v5.4 lvttl i/o module drive strength = 2 (12 ma) / high slew rate t dp input buffer 1.85 2.17 ns t py output buffer 3.87 4.55 ns t enzl enable to pad delay through the output buffer?high to z 4.08 4.79 ns t enzh enable to pad delay through the output buffer?z to high 3.34 3.93 ns t enlz enable to pad delay through the output buffer?low to z 1.98 1.99 ns t enhz enable to pad delay through the output buffer?z to low 2.31 2.31 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 3 (16 ma) / high slew rate t dp input buffer 1.85 2.17 ns t py output buffer 3.66 4.31 ns t enzl enable to pad delay through the output buffer?high to z 2.47 2.48 ns t enzh enable to pad delay through the output buffer?z to high 3.03 3.57 ns t enlz enable to pad delay through the output buffer?low to z 2.00 2.01 ns t enhz enable to pad delay through the output buffer?z to low 4.07 4.79 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns table 2-23 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-31 t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvttl i/o module drive strength = 4 (24 ma) / high slew rate t dp input buffer 1.85 2.17 ns t py output buffer 3.51 4.12 ns t enzl enable to pad delay through the output buffer?high to z 2.34 2.35 ns t enzh enable to pad delay through the output buffer?z to high 1.91 1.92 ns t enlz enable to pad delay through the output buffer?low to z 2.96 3.48 ns t enhz enable to pad delay through the output buffer?z to low 4.17 4.90 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-23 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-32 v5.4 2.5 v lvcmos low-voltage complementary metal-oxide semiconductor for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 2.5 v applications. it uses a 3.3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-24 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 0.7 1.7 3.6 0.4 2.0 12 ?12 figure 2-16 ? ac test loads table 2-25 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) 02.5 1.25 n/a 35 note: *measuring point = v trip r to v cc i for t plz /t pzl r to g nd for t phz /t pzh 35 pf for t pzh /t pzl 5 pf for t phz /t plz test point test point 35 pf for tristate r=1 k for t p d
rtax-s/sl radtolerant fpgas v5.4 2-33 timing characteristics table 2-26 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. lvcmos25 i/o module drive strength = 1 (6 ma) / low slew rate t dp input buffer 2.13 2.51 ns t py output buffer 21.66 25.46 ns t enzl enable to pad delay through the output buffer?high to z 22.81 26.81 ns t enzh enable to pad delay through the output buffer?z to high 20.47 24.07 ns t enlz enable to pad delay through the output buffer?low to z 4.53 4.53 ns t enhz enable to pad delay through the output buffer?z to low 4.92 4.92 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 2 (12 ma) / low slew rate t dp input buffer 2.13 2.51 ns t py output buffer 18.09 21.26 ns t enzl enable to pad delay through the output buffer?high to z 19.05 22.39 ns t enzh enable to pad delay through the output buffer?z to high 17.40 20.46 ns t enlz enable to pad delay through the output buffer?low to z 4.53 4.53 ns t enhz enable to pad delay through the output buffer?z to low 4.92 4.92 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns
rtax-s/sl radtolerant fpgas 2-34 v5.4 t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 3 (16 ma) / low slew rate t dp input buffer 2.13 2.51 ns t py output buffer 16.62 19.53 ns t enzl enable to pad delay through the output buffer?high to z 17.50 20.57 ns t enzh enable to pad delay through the output buffer?z to high 15.84 18.62 ns t enlz enable to pad delay through the output buffer?low to z 4.53 4.53 ns t enhz enable to pad delay through the output buffer?z to low 4.92 4.92 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 4 (24 ma) / low slew rate t dp input buffer 2.13 2.51 ns t py output buffer 15.66 18.41 ns t enzl enable to pad delay through the output buffer?high to z 16.49 19.38 ns t enzh enable to pad delay through the output buffer?z to high 15.09 17.74 ns t enlz enable to pad delay through the output buffer?low to z 4.53 4.53 ns table 2-26 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-35 t enhz enable to pad delay through the output buffer?z to low 4.92 4.92 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 1 (6 ma) / high slew rate t dp input buffer 2.13 2.51 ns t py output buffer 6.32 7.44 ns t enzl enable to pad delay through the output buffer?high to z 3.36 3.37 ns t enzh enable to pad delay through the output buffer?z to high 4.26 4.27 ns t enlz enable to pad delay through the output buffer?low to z 6.72 7.90 ns t enhz enable to pad delay through the output buffer?z to low 7.72 9.08 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-26 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-36 v5.4 lvcmos25 i/o module drive strength = 2 (12 ma) / high slew rate t dp input buffer 2.13 2.51 ns t py output buffer 4.43 5.21 ns t enzl enable to pad delay through the output buffer?high to z 2.61 2.62 ns t enzh enable to pad delay through the output buffer?z to high 2.99 3.00 ns t enlz enable to pad delay through the output buffer?low to z 6.72 7.90 ns t enhz enable to pad delay through the output buffer?z to low 7.72 9.08 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 3 (16 ma) / high slew rate t dp input buffer 2.13 2.51 ns t py output buffer 3.91 4.59 ns t enzl enable to pad delay through the output buffer?high to z 2.46 2.47 ns t enzh enable to pad delay through the output buffer?z to high 2.64 2.64 ns t enlz enable to pad delay through the output buffer?low to z 6.72 7.90 ns t enhz enable to pad delay through the output buffer?z to low 7.72 9.08 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns table 2-26 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-37 t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos25 i/o module drive strength = 4 (24 ma) / high slew rate t dp input buffer 2.13 2.51 ns t py output buffer 3.59 4.22 ns t enzl enable to pad delay through the output buffer?high to z 2.34 2.35 ns t enzh enable to pad delay through the output buffer?z to high 2.43 2.43 ns t enlz enable to pad delay through the output buffer?low to z 6.72 7.90 ns t enhz enable to pad delay through the output buffer?z to low 7.72 9.08 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-26 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-38 v5.4 1.8 v lvcmos low-voltage complementary metal-oxide semiconductor for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 1.8 v applicatio ns. it uses a 3.3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-27 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 0.2v cci 0.7v cci 2.1 0.2 v cci -0.2 8ma ?8ma figure 2-17 ? ac test loads table 2-28 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) 0 1.8 0.5v cci n/a 35 note: *measuring point = v trip r to v cc i for t plz /t pzl r to g nd for t phz /t pzh 35 pf for t pzh /t pzl 5 pf for t phz /t plz test point test point 35 pf for tristate r=1 k for t p d
rtax-s/sl radtolerant fpgas v5.4 2-39 timing characteristics table 2-29 ? worst-case military conditions v cca = 1.4 v, v cci = 1.7 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. lvcmos18 i/o module drive strength = 2 (2 ma) / low slew rate t dp input buffer 3.57 4.19 ns t py output buffer 33.79 39.72 ns t enzl enable to pad delay through the output buffer?high to z 35.58 41.83 ns t enzh enable to pad delay through the output buffer?z to high 26.65 31.33 ns t enlz enable to pad delay through the output buffer?low to z 4.74 4.75 ns t enhz enable to pad delay through the output buffer?z to low 5.02 5.02 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos18 i/o module drive strength = 3 (6 ma) / low slew rate t dp input buffer 3.57 4.19 ns t py output buffer 31.06 36.51 ns t enzl enable to pad delay through the output buffer?high to z 32.70 38.44 ns t enzh enable to pad delay through the output buffer?z to high 24.32 28.59 ns t enlz enable to pad delay through the output buffer?low to z 4.74 4.75 ns t enhz enable to pad delay through the output buffer?z to low 5.02 5.02 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns
rtax-s/sl radtolerant fpgas 2-40 v5.4 t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos18 i/o module drive strength = 4 (8 ma) / low slew rate t dp input buffer 3.57 4.19 ns t py output buffer 29.73 34.95 ns t enzl enable to pad delay through the output buffer?high to z 31.31 36.80 ns t enzh enable to pad delay through the output buffer?z to high 23.23 27.31 ns t enlz enable to pad delay through the output buffer?low to z 4.74 4.75 ns t enhz enable to pad delay through the output buffer?z to low 5.02 5.02 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos18 i/o module drive strength = 2 (2 ma) / high slew rate t dp input buffer 3.57 4.19 ns t py output buffer 6.54 7.69 ns t enzl enable to pad delay through the output buffer?high to z 3.06 3.07 ns t enzh enable to pad delay through the output buffer?z to high 4.41 4.41 ns t enlz enable to pad delay through the output buffer?low to z 7.04 8.27 ns t enhz enable to pad delay through the output buffer?z to low 7.88 9.26 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns table 2-29 ? worst-case military conditions v cca = 1.4 v, v cci = 1.7 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-41 t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos18 i/o module drive strength = 3 (6 ma) / high slew rate t dp input buffer 3.57 4.19 ns t py output buffer 5.55 6.52 ns t enzl enable to pad delay through the output buffer?high to z 2.85 2.86 ns t enzh enable to pad delay through the output buffer?z to high 3.74 3.75 ns t enlz enable to pad delay through the output buffer?low to z 7.04 8.27 ns t enhz enable to pad delay through the output buffer?z to low 7.88 9.26 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-29 ? worst-case military conditions v cca = 1.4 v, v cci = 1.7 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-42 v5.4 lvcmos18 i/o module drive strength = 4 (8 ma) / high slew rate t dp input buffer 4.97 5.85 ns t py output buffer 2.65 2.66 ns t enzl enable to pad delay through the output buffer?high to z 3.35 3.36 ns t enzh enable to pad delay through the output buffer?z to high 7.04 8.27 ns t enlz enable to pad delay through the output buffer?low to z 7.88 9.26 ns t enhz enable to pad delay through the output buffer?z to low 0.91 1.07 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.31 0.37 ns t sud data input setup 0.35 0.41 ns t sue enable input setup 0.00 0.00 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.39 0.39 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.37 0.37 ns t wasyn asynchronous pulse width 0.17 0.21 ns t reasyn asynchronous recovery time 0.00 0.00 ns t hasyn asynchronous removal time 0.31 0.37 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 4.97 5.85 ns table 2-29 ? worst-case military conditions v cca = 1.4 v, v cci = 1.7 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-43 1.5 v lvcmos (jesd8-11) low-voltage complementary metal-oxide semiconductor for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 1.5 v applicatio ns. it uses a 3.3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-30 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.5 0.35v cci 0.65v cci 1.95 0.4 v cci -0.4 8ma ?8ma figure 2-18 ? ac test loads table 2-31 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) 0 1.5 0.5v cci n/a 35 note: *measuring point = v trip r to v cc i for t plz /t pzl r to g nd for t phz /t pzh 35 pf for t pzh /t pzl 5 pf for t phz /t plz test point test point 35 pf for tristate r=1 k for t p d
rtax-s/sl radtolerant fpgas 2-44 v5.4 timing characteristics table 2-32 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. lvcmos15 i/o module drive strength = 1 (2 ma) / low slew rate t dp input buffer 3.93 4.62 ns t py output buffer 60.38 70.98 ns t enzl enable to pad delay through the output buffer?high to z 63.58 74.74 ns t enzh enable to pad delay through the output buffer?z to high 44.80 52.67 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 5.17 5.17 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 2 (4 ma) / low slew rate t dp input buffer 3.93 4.62 ns t py output buffer 53.29 62.65 ns t enzl enable to pad delay through the output buffer?high to z 56.12 65.97 ns t enzh enable to pad delay through the output buffer?z to high 37.88 44.53 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 5.17 5.17 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns
rtax-s/sl radtolerant fpgas v5.4 2-45 t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 3 (6 ma) / low slew rate t dp input buffer 3.93 4.62 ns t py output buffer 48.90 57.49 ns t enzl enable to pad delay through the output buffer?high to z 51.50 60.54 ns t enzh enable to pad delay through the output buffer?z to high 34.84 40.95 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 5.17 5.17 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 8 (4 ma) / low slew rate t dp input buffer 3.93 4.62 ns t py output buffer 47.21 55.49 ns t enzl enable to pad delay through the output buffer?high to z 49.71 58.43 ns t enzh enable to pad delay through the output buffer?z to high 33.18 39.01 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 5.17 5.17 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns table 2-32 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-46 v5.4 t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 1 (2 ma) / high slew rate t dp input buffer 3.93 4.62 ns t py output buffer 14.59 17.15 ns t enzl enable to pad delay through the output buffer?high to z 8.38 9.85 ns t enzh enable to pad delay through the output buffer?z to high 14.59 17.15 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 5.17 5.17 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 2 (4 ma) / high slew rate t dp input buffer 3.93 4.62 ns table 2-32 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-47 t py output buffer 9.12 10.73 ns t enzl enable to pad delay through the output buffer?high to z 3.69 3.70 ns t enzh enable to pad delay through the output buffer?z to high 9.12 10.73 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 8.12 9.54 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 3 (6 ma) / high slew rate t dp input buffer 3.93 4.62 ns t py output buffer 7.62 8.96 ns t enzl enable to pad delay through the output buffer?high to z 3.42 3.42 ns t enzh enable to pad delay through the output buffer?z to high 7.62 8.96 ns t enlz enable to pad delay through the output buffer?low to z 5.02 5.02 ns t enhz enable to pad delay through the output buffer?z to low 8.12 9.54 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns table 2-32 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas 2-48 v5.4 t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns lvcmos15 i/o module drive strength = 4 (8 ma) / high slew rate t dp input buffer 3.93 4.62 ns t py output buffer 6.60 7.76 ns t enzl enable to pad delay through the output buffer?high to z 3.12 3.13 ns t enzh enable to pad delay through the output buffer?z to high 4.45 4.46 ns t enlz enable to pad delay through the output buffer?low to z 7.45 8.76 ns t enhz enable to pad delay through the output buffer?z to low 8.12 9.54 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns table 2-32 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max.
rtax-s/sl radtolerant fpgas v5.4 2-49 3.3 v pci peripheral component interface for 3.3 v standard specifies support for 33 mh z and 66 mhz pci bus applications. it uses an lvttl input buffer and a push-pull output buffer. the input and output buffers are 5v tolerant with the aid of external components. the rtax-s/sl 3.3 v pci buffer is compliant with the pc i local bus specification rev. 2.1. ac loadings per pci specification except for tr istate. actel loading for tristate is in the figure below. table 2-33 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma pci ?0.5 0.3v cci 0.5v cci v cci +0.5 (per pci specification) figure 2-19 ? ac test loads table 2-34 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) (per pci spec) n/a 10 note: *measuring point = v trip r to v for t pl r to g nd for t ph cc i 10 pf g nd test point for d ata r = 25 35 pf for t pzl /t pzh 5 pf for t phz /t plz r to v cc i for t plz /t pzl r to g nd for t phz /t pzh test point for tristate r =1 k
rtax-s/sl radtolerant fpgas 2-50 v5.4 timing characteristics table 2-35 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. 3.3v pci i/o module timing t dp input buffer 1.72 2.02 ns t py output buffer 2.25 2.64 ns t enzl enable to pad delay through the output buffer?high to z 1.52 1.52 ns t enzh enable to pad delay through the output buffer?z to high 1.42 1.43 ns t enlz enable to pad delay through the output buffer?low to z 2.98 3.50 ns t enhz enable to pad delay through the output buffer?z to low 4.12 4.84 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas v5.4 2-51 table 2-36 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description ?1 speed std. speed units min. max. min. max. 3.3v pci-x i/o module timing t dp input buffer 1.72 2.02 ns t py output buffer 2.30 2.71 ns t enzl enable to pad delay through the output buffer?high to z 1.52 1.52 ns t enzh enable to pad delay through the output buffer?z to high 1.56 1.57 ns t enlz enable to pad delay through the output buffer?low to z 3.10 3.65 ns t enhz enable to pad delay through the output buffer?z to low 3.64 4.28 ns t ioclkq sequential clock-to-q for the input register 0.91 1.07 ns t ioclky clock-to-output y for the io ou tput register and the enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-52 v5.4 voltage-referenced i/o standards gtl+ gunning transceiver logic plus is a high-speed bus standard (j esd8-3). it requires a differ ential amplifier input buffer and an open drain output buffer. the v cci pin should be connected to 2.5 v or 3.3 v. note that 2.5 v gtl+ is not supported across the full military temperature range. ac loadings timing characteristics table 2-37 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma n/a v ref -0.1 v ref +0.1 n/a 0.6* na na na note: for high temperature of 125c only, v ol limits are 700 mv, for all othe r temperatures 600 mv applies. figure 2-20 ? ac test loads table 2-38 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -0.2 v ref +0.2 v ref 1.0 10 note: *measuring point = v trip test point 10 pf 25 v tt table 2-39 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 3.3 v gtl+ i/o module timing t dp input buffer 2.01 2.36 ns t py output buffer 1.26 1.49 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas v5.4 2-53 hstl class i high-speed transceiver logic is a genera l-purpose high-speed 1.5 v bus standard (eia/jesd8-6). the rtax-s/sl devices support class i. this requires a differential amplifier input buffer and a push-pull output buffer. ac loadings timing characteristics table 2-40 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 v ref -0.1 v ref +0.1 3.6 0.4 v cc -0.4 8 ?8 figure 2-21 ? ac test loads table 2-41 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -0.5 v ref +0.5 v ref 0.75 20 note: *measuring point = v trip test point 20 pf 50 v tt table 2-42 ? worst-case military conditions v cca = 1.4 v, v cci = 1.4 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 1.5 v hstl class i i/o module timing t dp input buffer 2.12 2.49 ns t py output buffer 5.35 6.29 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-54 v5.4 sstl2 stub series terminated logic for 2.5 v is a general-purp ose 2.5 v memory bus standard (jesd8-9). the rtax-s/sl devices support both classes of this standard. this requires a differential amplifier input buffer and a push-pull output buffer. class i ac loadings timing characteristics table 2-43 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.57 v ref +0.57 7.6 ?7.6 figure 2-22 ? ac test loads table 2-44 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -0.75 v ref +0.75 v ref 1.25 30 note: *measuring point = v trip test point 30 pf 50 25 v tt table 2-45 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 2.5 v sstl2 class i i/o module timing t dp input buffer 2.14 2.52 ns t py output buffer 2.61 3.07 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas v5.4 2-55 class ii ac loadings timing characteristics table 2-46 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.8 v ref +0.8 15.2 ?15.2 figure 2-23 ? ac test loads table 2-47 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -0.75 v ref +0.75 v ref 1.25 30 note: *measuring point = v trip test point 30 pf 25 25 v tt table 2-48 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 2.5 v sstl2 class ii i/o module timing t dp input buffer 2.22 2.61 ns t py output buffer 2.61 3.07 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-56 v5.4 sstl3 stub series terminated logic for 3.3 v is a general-purp ose 3.3 v memory bus standard (jesd8-8). the rtax-s/sl devices support both classes of this standard. this requires a differential amplifier input buffer and a push-pull output buffer. class i ac loadings timing characteristics table 2-49 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.6 v ref +0.6 8 ?8 figure 2-24 ? ac test loads table 2-50 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -1.0 v ref +1.0 v ref 1.50 30 note: *measuring point = v trip test point 30 pf 50 25 v tt table 2-51 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 3.3 v sstl3 class i i/o module timing t dp input buffer 2.09 2.46 ns t py output buffer 2.55 2.99 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas v5.4 2-57 class ii ac loadings timing characteristics table 2-52 ? dc input and output levels v il v ih v ol v oh i ol i oh min,v max,v min,v max,v max,v min,v ma ma ?0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.8 v ref +0.8 16 ?16 figure 2-25 ? ac test loads table 2-53 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) v ref (typ) (v) c load (pf) v ref -1.0 v ref +1.0 v ref 1.50 30 note: *measuring point = v trip test point 30 pf 25 25 v tt table 2-54 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. 3.3 v sstl3 class ii i/o module timing t dp input buffer 2.17 2.55 ns t py output buffer 2.55 2.99 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-58 v5.4 differential standards physical implementation implementing differential i/o standards requires the configuration of a pair of exte rnal i/o pads, resulting in a single internal signal. to fa cilitate construction of the differential pair, a single i/o cluster contains the resources for a pair of i/os . configuration of the i/o cluster as a differential pair is handled by actel's designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output register (outreg), and enable register (enreg). however, there is no support for bidirectional i/os or tristates with these standards. lvds low-voltage differential sign al (ansi/tia/eia-644) is a high-speed differential i/o st andard. it requires that one data bit is carried through two signal lines, so two pins are needed. it also requir es an external resistor termination. the voltage swing between these two signal lines is approximately 350 mv. the lvds circuit consists of a differential driver connected to a terminated receiver through a constant- impedance transmission line. the receiver is a wide- common-mode-range differ ential amplifier. the common-mode range is from 0.2 v to 2.2 v for a differential input with 400 mv swing. to implement the driver for the lvds circuit, drivers from two adjacent i/o cells are used to generate the differential signals (note that the driver is not a current- mode driver). this driver provides a nominal constant current of 3.5 ma. when this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mv is developed across the resistor. the direction of the current flow is controlled by the data fed to the driver. an external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mv. therefore, four external resistors are required, three for the driver and one for the receiver. figure 2-26 ? lvds circuit 140 100 zo = 50 zo = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga table 2-55 ? dc input and output levels dc parameter descripti on min. typ. max. units v cci 1 supply voltage 2.375 2.5 2.625 v v ol output low voltage 0.9 1.075 1.25 v v oh output high voltage 1.25 1.425 1.6 v v i input voltage 0 2.925 v v odiff differential output voltage 250 350 450 mv v ocm output common mode voltage 1.125 1.25 1.375 v v icm 2 input common mode voltage 0.2 1.25 2.2 v v idiff differential input voltage 100 350 mv notes: 1. +/- 5% 2. differential input voltage = 400 mv.
rtax-s/sl radtolerant fpgas v5.4 2-59 ac loadings for ac test loads, see the above lvds circuit. timing characteristics table 2-56 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 1.2-0.125 1.2+0.125 1.2 n/a note: *measuring point = v trip table 2-57 ? worst-case military conditions v cca = 1.4 v, v cci = 2.3 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. lvds i/o module timing t dp input buffer 2.00 2.35 ns t py output buffer 2.54 2.99 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-60 v5.4 lvpecl low-voltage positive emitter-coupled logi c (lvpecl) is another differential i/o st andard. it requires that one data bit is carried through two signal lines. like lvds, two pins are need ed. it also requires external resistor termination. the voltage swing between th ese two signal lines is approximately 850 mv. the lvpecl circuit is similar to the lvds scheme. it requires four external resistors, three for the driver and one for the receiver. the values for the three driver resistors are differ ent from that of lvds, since the output voltage levels are different. please note that the v oh levels are 200 mv below the standard lvpecl levels. ac loadings for ac test loads, see the above lvpecl circuit. figure 2-27 ? lvpecl circuit table 2-58 ? dc input and output levels dc parameter min. typ. max. units min. max. min. max. min. max. v cci 3?3.3?3.6? v v oh 1.8 2.11 1.92 2.28 2.13 2.41 v v ol 0.96 1.27 1.06 1.43 1.3 1.57 v v ih 1.49 2.72 1.49 2.72 1.49 2.72 v v il 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 ? 0.3 ? 0.3 ? v table 2-59 ? ac waveforms, measuring po ints, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 1.6-0.3 1.6+0.3 1.6 n/a note: *measuring point = v trip 187 100 zo = 50 zo = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga
rtax-s/sl radtolerant fpgas v5.4 2-61 timing characteristics table 2-60 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. lvpecl i/o module timing t dp input buffer 1.83 2.15 ns t py output buffer 2.45 2.88 ns t iclkq clock-to-q for the i/o input register 0.91 1.07 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.91 1.07 ns t sud data input setup 0.31 0.37 ns t sue enable input setup 0.35 0.41 ns t hd data input hold 0.00 0.00 ns t he enable input hold 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 ns t reasyn asynchronous recovery time 0.17 0.21 ns t hasyn asynchronous removal time 0.00 0.00 ns t clr asynchronous clear-to-q 0.31 0.37 ns t preset asynchronous preset-to-q 0.31 0.37 ns
rtax-s/sl radtolerant fpgas 2-62 v5.4 module specifications c-cell introduction the c-cell is one of the two logic module types in the rtax-s/sl architecture. it is the combinatorial logic resource in the rtax-s/sl device. the rtax-s/sl architecture implements a ne w combinatorial cell that is an extension of the c-cell implemented in the a54sx-a family. the main enhancemen t of the new c-cell is the addition of carry-chain logic. the c-cell can be used in a carry-chain mode to construct arithmetic functions. if carry-c hain logic is not required, it can be disabled. the c-cell features the following ( figure 2-28 ): ? eight-input mux (data: d0-d3, select: a0, a1, b0, b1). user signals can be routed to any one of these inputs. any of the c-cell inputs (d0-d3, a0, a1, b0, b1) can be tied to one of the four routed clocks (clke/f/g/h). ? inverter (db input) can be used to drive a complement signal of any of the inputs to the c-cell. ? a carry input and a carry output. the carry input signal of the c-cell is the carry output from the c-cell directly to the north. ? carry connect for carry- chain logic with a signal propagation time of less than 0.1 ns. ? a hardwired connection (direct connect) to the adjacent r-cell (register ce ll) for all c-cells on the east side of a supercluster with a signal propagation time of less than 0.1 ns. this layout of the c-cell (and the c-cell cluster) enables the implementation of over 4, 000 functions of up to five bits. for example, two c-cells can be used together to implement a four-input xor function in a single cell delay. the carry-chain configuratio n is handled automatically for the user with the extensive actel macro library. refer to the actel antifuse macro library guide for a complete listing of available rtax-s/sl macros. figure 2-28 ? c-cell 1 0 d1 d3 b1 b0 d0 d2 db a1 a0 cfn fci fco y 0 0 0 0 1 1 1 1
rtax-s/sl radtolerant fpgas v5.4 2-63 timing model and waveforms timing characteristics figure 2-29 ? c-cell timing model and waveforms y, fco y, fco gnd v cca 50 % 50 % 50 % 50 % gnd gnd 50 % 50 % a, b, d, fci t pd , t pdc v cca v cca t pd , t pdc t pd , t pdc t pd , t pdc table 2-61 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. c-cell propagation delays t pd any input to output 0.95 1.11 ns t pdc any input to carry chain output (fco) 0.70 0.82 ns t pdb any input thorough db when 1 input is used 1.49 1.75 ns t ccy input carry chain (fci) to y 0.76 0.90 ns t cc input carry chain (fci) to carry chain output (fco) 0.10 0.12 ns
rtax-s/sl radtolerant fpgas 2-64 v5.4 carry-chain logic the rtax-s/sl dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. to implement the ca rry-chain logic, two c-cells in a cluster are connected together so the fco (i.e., carry out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay from the fci (i.e., carry in) into the two-bit cluster. the two-bit carry logic is shown in figure 2-30 . the fci of one c-cell pair is driven by the fco of the c-cell pair immediately above it. similarly, the fco of one c-cell pair, drives the fc i input of the c-cell pair immediately below it ( figure 1-5 on page 1-3 and figure 2-31 on page 2-65 ). the carry-chain logic is sele cted via the cfn input. when carry logic is not required, th is signal is deasserted to save power. again, this configuration is handled automatically for the user through the actel macro library. the signal propagation delay between two c-cells in the carry-chain sequence is 0.1 ns. figure 2-30 ? rtax-s/sl two-bit carry logic 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 dcout d0 d2 db a1 a0 y fco y d0 d2 db a1 a0 d1 d3 b1 b0 d1 d3 b1 b0 cfn cfn fci
rtax-s/sl radtolerant fpgas v5.4 2-65 timing characteristics refer to the c-cell timing characteristics in table 2-61 on page 2-63 for more information on carry-chain timing. note: the carry-chain sequence ca n end on either c-cell. figure 2-31 ? carry-chain sequencing of c-cells dcin dcout c-cell1 c-cell2 dcout r-cell1 dcin c-cell (2n-1) c-cell2n dcout r-celln cdin n-2 clusters fco 2n fci (2n-1) fci 5 fco 4 fci 3 fco 2 fci 1
rtax-s/sl radtolerant fpgas 2-66 v5.4 r-cell introduction the r-cell, the sequential logi c resource of the rtax-s/sl devices, is the second logic module type in the rtax-s/sl family architecture. the rtax-s/sl r-cell is an enhanced version of the a54sx-a r-cell. it includes additional clock inputs for all eight global resources of the rtax-s/sl architecture as well as global presets and clears ( figure 2- 32 ). the main features of the r-cell include the following: ? direct connection to th e adjacent logic module through the hardwired connection dcin. dcin is driven by the dcout of an adjacent c-cell via the direct-connect routing resource, providing a connection with less than 0.1 ns of routing delay. ? the r-cell can be used as a standalone flip-flop. it can be driven by any c- cell or i/o modules through the regular routing structure (using din as a routable data input). this gives the option of using the r-cell as a 2:1 muxed flip-flop as well. ? provision of data enable-input (s0). ? independent active low asynchronous clear (clr). ? independent active lo w asynchronous preset (pset). if both clr and pset are low, clr has higher priority. ? clock can be driven by any of the following (ckp selects clock polarity): ? one of the four high performance hardwired fast clocks (hclks) ? one of the four routed clocks (clks) ? user signals ? global power-on clear (gclr) and preset (gpset), which drive each flip-flop on a chip-wide basis. ? when the global set fuse option in the designer software is unchecked (by default), gclr = 0 and gpset =1 at device power-up. when the option is checked, gclr = 1 and gpset= 0. both pins ar e pulled high when the device is in user mode. ? s0, s1, pset, and clr can be driven by routed clocks clke/f/g/h or user signals. ? din and s1 can be driven by user signals. as with the c-cell, the conf iguration of the r-cell to perform various functions is handled automatically for the user through actel's extensive macro library (please see the actel macro library guide for a complete listing of available rtax-s/sl macros). figure 2-32 ? r-cell clr gclr pre gpre y s1 s0 cks dcin din (user signals) hclka/b/c/d clke/f/g/h internal logic ckp seu enhanced d-ff
rtax-s/sl radtolerant fpgas v5.4 2-67 seu hardened d flip-flop (dff) in order to meet the stringent seu requirements of a let th greater than 37 mev-cm 2 /mg, the internal design of the r-cell was modified without changing the functionality of the cell. figure 2-33 illustrates a simp lified representation of how the d flip-flop in the supercluster is implemented in the rtax-s/sl architecture. the flip-flop consists of a master and a slave latch gated by opposite edges of the clock. each latch is constructed by feeding back the output to the input stage. the potential problem in a space environment is that either of the latches can change state when hit by a particle with enough energy. to achieve the seu requiremen ts, the d flip-flop in the rtax-s/sl r-cell is enhanced ( figure 2-34 ). both the master and slave "latches" are actually implemented with three latches. the asynchronous self-correcting feedback paths of each of the three latches is voted with the outputs of the other two latches. if one of the three latches is struck by an ion a nd starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. care was taken in the layout to ensu re that a single ion strike could not affect more than one latch. figure 2-35 on page 2-68 is a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip-flop. the inputs to each of the three latches are independently controllable, so the voting circuitry in the asynchronous self-correcting feedback paths can be tested exhaustively. this testing is performed on an unprogrammed array during wafer sort, final test, and post-burn-in test. this test circuitry cannot be used to test the flip-flops once the device has been programmed. figure 2-33 ? rtax-s/sl r-cell implementation of d flip-flop figure 2-34 ? rtax-s/sl r-cell implementation of d flip-flop using voter gate logic d clk clk q q clk clk d clk voter gate clk clk clk clk clk
rtax-s/sl radtolerant fpgas 2-68 v5.4 timing models and waveforms figure 2-35 ? rtax-s/sl r-cell implementa tion ? test circuitry tst1 clk d q voter gate tst2 tst3 test circuitry figure 2-36 ? r-cell delays e d q c lr pre s et c lk t s ue t he t s ud t hd t r c o t wa s yn t ha s yn t c lr t rea s yn t c pwhl t c pwlh t pre s et t wa s yn t ha s yn t rea s yn
rtax-s/sl radtolerant fpgas v5.4 2-69 timing characteristics buffer module introduction an additional resource inside each supe rcluster is the buffer (b) module ( figure 1-4 on page 1-3 ). when a fanout constraint is applied to a design, the synthe sis tool inserts buffers as needed. the buffer module has been added to the rtax-s/sl ar chitecture to avoid logic duplication resulting from the hard fanout constraints. the router utilizes this logic re source to save area and reduce loading an d delays on medium-to-high-fanout nets. timing models and waveforms timing characteristics table 2-62 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. r-cell propagation delays t rco sequential clock to q 0.96 1.12 ns t clr asynchronous clear to q 0.63 0.74 ns t preset asynchronous preset to q 0.76 0.89 ns t sud ff data input setup 0.21 0.25 ns t sue ff enable input setup 0.21 0.25 ns t hd ff data hold 0.00 0.00 ns t he ff enable hold time 0.00 0.00 ns t wasyn asynchronous pulse width 0.48 0.48 ns t reasyn asynchronous recovery time 0.00 0.00 ns t hasyn asynchronous removal time 0.00 0.00 ns t cpwhl clock pulse width high to low 0.36 0.36 ns t cpwlh clock pulse width low to high 0.36 0.36 ns figure 2-37 ? buffer module timing model in out figure 2-38 ? buffer module waveform out gnd 50 % 50 % 50 % 50 % gnd in v cca v cca t bfpd t bfpd table 2-63 ? worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c parameter description '?1' speed 'std.' speed units min. max. min. max. t bfpd any input to output y 0.17 0.20 ns
rtax-s/sl radtolerant fpgas 2-70 v5.4 routing specifications routing resources the routing structure found in rtax-s/sl devices enables any logic module to be connected to any other logic module while retaining high performance. there are multiple paths and routing resources that can be used to route one logic module to another, both within a supercluster and else where on the chip. there are four primary types of routing within the rtax-s/ sl architecture: directconnect, carryconnect, fastconnect and vertical and horizontal routing. directconnect directconnects provide a high-speed connection between an r-cell and its adjacent c-cell ( figure 2-39 ). this connection can be made from dcout of the c-cell to dcin of the r-cell by conf iguring of the s1 line of the r-cell. this provides a conne ction that does not require an antifuse and has a delay of less than 0.1 ns. carryconnect carryconnects are used to build carry chains for arithmetic functions ( figure 2-39 ). the fco output of the right c-cell of a two-c-cell cluster drives the fci input of the left c-cell in the two-c-cell cluster immediately below it. this pattern continues down both sides of each supercluster column. similar to the directconnects, carryconnects can be built without an antifuse connection. this connection has a delay of less than 0.1 ns from the fco of one two-c-cell cluster to the fci of the two-c-cell cluster immediately below it (see the "carry-chain logic" on page 2-64 for more information). fastconnect for high-speed routing of logic signals, fastconnects can be used to build a short distance connection using a single antifuse ( figure 2-40 on page 2-71 ). fastconnects provide a maximum delay of 0.4 ns. the outputs of each logic module connect directly to the output tracks within a supercluster. signal s on the output tracks can then be routed through a single antifuse connection to drive the inputs of logic modules either within one supercluster or in the supercluster immediately below it. vertical and horizontal routing vertical and horizontal tracks provide both local and long distance routing ( figure 2-41 on page 2-71 ). these tracks are composed of both short-distance, segmented routing and across-chip rout ing tracks (segmented at core tile boundaries). th e short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. these short-distance routing tracks can be used within and between superclusters or between modules of non- adjacent superclusters. they can be connected to the output tracks and to any logic module input (r-cell, c-cell, buffer, and tx module). figure 2-39 ? directconnect and carryconnect
rtax-s/sl radtolerant fpgas v5.4 2-71 the across-chip horizontal and vertical routing provides long-distance, routing resources. these resources interface with the rest of the routing structures through the rx and tx modules ( figure 2-41 on page 2-71 ). the rx module is used to drive signals from the across-chip horizontal and vertical routing to the output tracks within the supercluster. the tx module is used to drive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from output tracks. the tx module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. figure 2-40 ? fastconnect routing figure 2-41 ? horizontal and vertical tracks
rtax-s/sl radtolerant fpgas 2-72 v5.4 timing characteristics table 2-64 ? rtax250s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed unit min. max. min. max. predicted routing delays t dc direct connect 0.08 0.07 ns t fc fast connect f01 0.24 0.29 ns t rd1 fanout 1 0.66 0.77 ns t rd2 fanout 2 0.84 0.99 ns t rd3 fanout 3 1.07 1.25 ns t rd4 fanout 4 1.38 1.62 ns t rd5 fanout 5 1.45 1.7 ns t rd6 fanout 6 2.08 2.44 ns t rd7 fanout 7 2.26 2.66 ns t rd8 fanout 8 2.44 2.87 ns t rd9 fanout 9 2.87 3.37 ns t rd10 fanout 10 3.3 3.88 ns table 2-65 ? rtax1000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed unit min. max. min. max. predicted routing delays t dc direct connect 0.08 0.07 ns t fc fast connect f01 0.24 0.29 ns t rd1 fanout 1 0.66 0.77 ns t rd2 fanout 2 0.84 0.99 ns t rd3 fanout 3 1.07 1.25 ns t rd4 fanout 4 1.38 1.62 ns t rd5 fanout 5 1.45 1.7 ns t rd6 fanout 6 2.08 2.44 ns t rd7 fanout 7 2.26 2.66 ns t rd8 fanout 8 2.44 2.87 ns t rd9 fanout 9 2.87 3.37 ns t rd10 fanout 10 3.3 3.88 ns
rtax-s/sl radtolerant fpgas v5.4 2-73 table 2-66 ? rtax2000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed unit min. max. min. max. predicted routing delays t dc direct connect 0.08 0.07 ns t fc fast connect f01 0.24 0.29 ns t rd1 fanout 1 0.66 0.77 ns t rd2 fanout 2 0.84 0.99 ns t rd3 fanout 3 1.07 1.25 ns t rd4 fanout 4 1.38 1.62 ns t rd5 fanout 5 1.45 1.70 ns t rd6 fanout 6 2.08 2.44 ns t rd7 fanout 7 2.26 2.66 ns t rd8 fanout 8 2.44 2.87 ns t rd9 fanout 9 2.87 3.37 ns t rd10 fanout 10 3.30 3.88 ns table 2-67 ? rtax4000s (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description 'std.' speed unit min. max. predicted routing delays t dc direct connect 0.07 ns t fc fast connect f01 0.29 ns t rd1 fanout 1 0.77 ns t rd2 fanout 2 0.99 ns t rd3 fanout 3 1.25 ns t rd4 fanout 4 1.62 ns t rd5 fanout 5 1.7 ns t rd6 fanout 6 2.44 ns t rd7 fanout 7 2.66 ns t rd8 fanout 8 2.87 ns t rd9 fanout 9 3.37 ns t rd10 fanout 10 3.88 ns
rtax-s/sl radtolerant fpgas 2-74 v5.4 global resources one of the most important aspects of any fpga architecture is its global re sources or clocks. the rtax-s/ sl family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other fpga architectures. in addition, these global resources have been hardened to improve seu performance. the rtax-s/sl architecture contains two types of global resources, the hclk (hardwired clock) and clk (routed clock). every rtax-s/sl devi ce is provided with four hclks and four clks for a total of eight clocks, regardless of device density. hardwired clocks the hardwired (hclk) is a low-skew network that can directly drive the clock inputs of all sequential modules (r-cells, i/o registers and em bedded ram/fifos) in the device with no antifuse in the path. all four hclks are available everywhere on the chip. timing characteristics table 2-68 ? rtax250s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hckl input low to high 2.76 3.24 ns t hckh input high to low 2.94 3.46 ns table 2-69 ? rtax250s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hpwh minimum pulse width high 0.77 0.77 ns t hpwl minimum pulse width low 0.26 0.26 ns f hmax 1 maximum frequency 649 649 mhz note: *f hmax = 1000/(2*(max(t hpwh ,t hpwl ))) table 2-70 ? rtax1000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hckl input low to high 3.65 4.29 ns t hckh input high to low 3.48 4.09 ns table 2-71 ? rtax1000s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hpwh minimum pulse width high 0.86 0.86 ns t hpwl minimum pulse width low 0.31 0.31 ns f hmax 1 maximum frequency 581 581 mhz note: *f hmax = 1000/(2*(max(t hpwh ,t hpwl )))
rtax-s/sl radtolerant fpgas v5.4 2-75 table 2-72 ? rtax2000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hckl input low to high 3.65 4.29 ns t hckh input high to low 3.48 4.09 ns table 2-73 ? rtax2000s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t hpwh minimum pulse width high 0.77 0.77 ns t hpwl minimum pulse width low 0.26 0.26 ns f hmax 1 maximum frequency 649 649 mhz note: *f hmax = 1000/(2*(max(t hpwh ,t hpwl ))) table 2-74 ? rtax4000s (worst-case mi litary conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description 'std.' speed units min. max. t hckl input low to high 4.37 ns t hckh input high to low 4.16 ns table 2-75 ? rtax4000s worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description 'std.' speed units min. max. t hpwh minimum pulse width high tbd ns t hpwl minimum pulse width low tbd ns f hmax 1 maximum frequency tbd mhz note: *f hmax = 1000/(2*(max(t hpwh ,t hpwl )))
rtax-s/sl radtolerant fpgas 2-76 v5.4 routed clocks the routed clock (clk) is a low-skew ne twork that can drive the clock inputs of all sequential modules in the device (logically equivalent to the hclk), but has the added flexibilit y in that it can drive the s0 (enable), s1, pset, and clr input of a register (r-cells and i/o register s) as well as any of the in puts of any c-cell in the de vice. this allows clks to be used not only as clocks, but also for other global signal s or high fanout nets. all four clks are available everywhere on the chip. timing characteristics table 2-76 ? rtax250s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rckl input low to high 2.78 3.26 ns t rckh input high to low 2.92 3.43 ns t rcksw maximum skew ? 16 loads 1.40 1.65 ns maximum skew ? 24 loads 1.81 2.13 ns table 2-77 ? rtax250s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rpwh minimum pulse width high 0.79 0.79 ns t rpwl minimum pulse width low 0.27 0.27 ns f rmax 1 maximum frequency 633 633 mhz note: *f rmax = 1000/(2*(max(t rpwh ,t rpwl ))) table 2-78 ? rtax1000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rckl input low to high 3.71 4.37 ns t rckh input high to low 3.54 4.16 ns t rcksw maximum skew ? 16 loads 1.39 1.64 ns maximum skew ? 24 loads 1.80 2.12 ns maximum skew ? 36 loads 1.87 2.20 ns table 2-79 ? rtax1000s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rpwh minimum pulse width high 1.04 1.04 ns t rpwl minimum pulse width low 0.33 0.33 ns f rmax 1 maximum frequency 481 481 mhz note: *f rmax = 1000/(2*(max(t rpwh ,t rpwl )))
rtax-s/sl radtolerant fpgas v5.4 2-77 table 2-80 ? rtax2000s/sl (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rckl input low to high 3.71 4.37 ns t rckh input high to low 3.54 4.16 ns t rcksw maximum skew ? 16 loads 1.39 1.64 ns maximum skew ? 24 loads 1.80 2.12 ns maximum skew ? 36 loads 2.12 2.49 ns table 2-81 ? rtax2000s/sl worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description '?1' speed 'std.' speed units min. max. min. max. t rpwh minimum pulse width high 0.79 ns t rpwl minimum pulse width low 0.27 ns f rmax 1 maximum frequency 633 mhz note: *f rmax = 1000/(2*(max(t rpwh ,t rpwl ))) table 2-82 ? rtax4000s (worst-case mi litary conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description 'std.' speed units min. max. t rckl input low to high 6.41 ns t rckh input high to low 6.19 ns t rcksw maximum skew ? 16 loads 1.65 ns maximum skew ? 24 loads 2.11 ns maximum skew ? 36 loads 2.16 ns table 2-83 ? rtax4000s worst-case mpw (v cca = 1.575 v, v cci = 3.6 v, t j = 125c) parameter description 'std.' speed units min. max. t rpwh minimum pulse width high tbd ns t rpwl minimum pulse width low tbd ns f rmax 1 maximum frequency tbd mhz note: *f rmax = 1000/(2*(max(t rpwh ,t rpwl )))
rtax-s/sl radtolerant fpgas 2-78 v5.4 global resource distribution at the root of each global resource is a clockdistbuffer (cdb). there are two groups of four cdbs for every device. one group, located at the cent er of the north edge (in the i/o ring) of the chip, sources the four hclks. the second group, located at the center of the south edge (again in the i/o ring), sources the four clks ( figure 2-42 ). regardless of the type of gl obal resource, hclk or clk, each of the eight resources reach the clocktiledist (ctd) cluster located at the center of every core tile with zero skew. from the clocktiledist cl uster, all four hclks and four clks are distributed through the core tile ( figure 2-43 ). figure 2-42 ? clockdistbuffer group figure 2-43 ? example of hclk and clk dis tributions on the rtax2000s/sl cdb cluster cdb cluster pn pn pn pn pn pn pn pn hclka hclkb hclkc hclkd clke clkf clkg clkh cdb cluster hclk clk cdb cluster 4 4 clocktiledist cluster
rtax-s/sl radtolerant fpgas v5.4 2-79 the clocktiledist cluster contains an hclkmux (hm) module for each of the four hclk trees and a clkmux (cm) module for each of the clk trees. the hclk branches then pr opagate horizontally through the middle of the core tile to hclkcoldist (hd) modules in every supercluster column. the clk branches propagate vertically through the center of the core tile to clkrowdist (rd) modules in every supercluster row. together, the hclk and clk branches provide for a low- skew global fanout within the core tile ( figure 2-44 and figure 2-45 ). figure 2-44 ? ctd, cd, and hd module layout figure 2-45 ? hclk and clk di stribution with in a core tile
rtax-s/sl radtolerant fpgas 2-80 v5.4 the hm and cm modules can select between: ? the hclk or clk source ? a local signal routed on generic routing resources this allows each core t ile to have eight clocks independent of the other core tiles in the device. both hclk and clk are se gmentable, meaning that individual branches of the global resource can be used independently. like the hm and cm module s, the hd and rd modules can select between: ? the hclk or clk source from the hm or cm module, respectively ? a local signal routed on generic routing resources again, an unused input can be tied to ground for power savings. the rtax-s/sl architecture is capable of supporting a large number of local cloc ks ? 24 segments per hclk driving north-south and 28 segments per clk driving east-west per core tile. actel designer software?s place-and-route takes advantage of the segmente d clock structure found in rtax-s/sl devices by turning off any unused clock segments. this results in not only better performance but also lower power consumption. future releases of designer will give the user greater contro l over these individual clock segments. global resource access macros global resources can be driven by one of three sources: external pad(s) or an intern al net. these connections can be made by using one of two types of macros: clkbuf and clkint. clkbuf and hclkbuf clkbuf (hclkbuf) is used to drive a clk (hclk) from external pads. these macros can be used either generically or with the specific i/o standard desired (e.g. clkbuf_lvcmos25, hclkbuf_lvds, etc.) ( figure 2-46 ). package pins clkep and clken are associated with clke; package pins hclkap and hclkan are associated with hclka, etc. note that when clkbuf (h clkbuf) is used with a single-ended i/o standard, it must be tied to the p- pad of the clk (hclk) package pin. in this case, the clk (hclk) n-pad can be used for user signals. clkint and hclkint clkint (hclkint) is used to access the clk (hclk) resource internally from the user signals ( figure 2-47 ) . figure 2-46 ? clkbuf and hclkbuf figure 2-47 ? clkint and hclkint p n clkbuf hclkbuf clock network clkint hclkint clock network logic
rtax-s/sl radtolerant fpgas v5.4 2-81 embedded memory the rtax-s/sl architecture provides extensive, high- speed memory resources to the user. each 4,608-bit block of ram contains its own embedded fifo controller, allowing the user to config ure each block as either ram or fifo. to meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write oper ations. however, the read and write clocks are completely independent, and each may operate beyond 500 mhz. no additional core logic resources are required to cascade the address and data buses when cascading different ram blocks. dedicated routing runs along each column of ram to facilitate cascading. the rtax-s/sl memory bloc k includes dedicated fifo control logic to generate in ternal addresses and external flag logic (full, empty, afull, aempty). since read and write operations can occur as ynchronously to one another, special control circuitry is included to prevent metastability, overflow, a nd underflow. a block diagram of the memory module is illustrated in figure 2-48 . during ram operation, read (ra) and write (wa) addresses are sourced by user logic and the fifo controller is ignored. in fifo mode, the internal addresses are generated by the fifo controller and routed to the ram array by internal muxes. enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. when cascading memory blocks, the bussed signals wa, wd, wen, ra, rd, and ren are internally linked to eliminate external routing congestion. ram each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. this allows built-in bus width conversion ( table 2-84 ). each block has independent read and write ports, which enable simultaneous read and write operations. simultaneous read and write operations to the same address is not supported. figure 2-48 ? rtax-s/sl memory module ra [k:0] rd [(n-1):0] ren rclk wd [(m-1):0] wa [j:0] wen wclk pipe rw [2:0] ww [2:0] table 2-84 ? memory block wxd options data-word (in bits) depth address bus data bus 1 4,096 ra/wa[11:0] rd/wd[0] 2 2,048 ra/wa[10:0] rd/wd[1:0] 4 1,024 ra/wa[9:0] rd/wd[3:0] 9 512 ra/wa[8:0] rd/wd[8:0] 18 256 ra/wa[7:0] rd/wd[17:0] 36 128 ra/wa[6:0] rd/wd[35:0]
rtax-s/sl radtolerant fpgas 2-82 v5.4 clocks the rclk and the wclk have independent source polarity selection and can be sourced by any global or local signal. ram configurations the rtax-s/sl architecture allows the read side and write side of rams to be organized independently, allowing for bus conversion. for example, the write side can be set to 256x18 and the read side to 512x9. both the write width and read width for the ram blocks can be specified independently and changed dynamically with the ww (write width) and rw (read width) pins. the available dxw configur ations are: 128x36, 256x18, 512x9, 1kx4, 2kx2, and 4kx1. the allowable rw and ww values are shown in table 2-86 . when widths of one, two, and four are selected, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operat ions. the ninth bit is not accessible. conversely, when writing four-bit values and reading nine-bit values, the ni nth bit of a read operation will be undefined. note that the ram blocks employ little-endian byte order for read and write operations. table 2-85 ? ram signal description signal direction description wclk input write clock (can be active on either edge). wa[j:0] input write address bus.the valu e j is dependent on the ram configuration and the number of cascaded memory blocks. the valid range for j is from 6 to15. wd[m-1:0] input write data bus. the value m is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. rclk input read clock (can be active on either edge). ra[k:0] input read address bus. the value k is dependent on the ram configuration and the number of cascaded memory blocks. the valid range for k is from 6 to 15. rd[n-1:0] output read data bus. the value n is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. ren input read enable. when this signal is valid on the active edge of the clock, data at location ra will be driven onto rd. wen input write enable. when this signal is valid on the active edge of the clock, wd data will be written at location wa. rw[2:0] input width of the read operation dataword. ww[2:0] input width of the write operation dataword. pipe input sets the pipeline option to be on or off. table 2-86 ? allowable rw and ww values rw(2:0) ww(2:0) d x w 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101 101 128x36 11x 11x reserved
rtax-s/sl radtolerant fpgas v5.4 2-83 modes of operation there are two read mode s and one write mode: ? read nonpipelined (synchronous ? one clock edge): in the standard read mode, new data is driven onto the rd bus in the clock cycle immediately following ra and ren valid. the read address is registered on the read-por t active-clock edge and data appears at read-d ata after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous ? two clock edges): the pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher freque ncy. the read-address is registered on the read-port active-clock edge, and the read data is registered and appears at rd after the second read clock edge. setting pipe to on enables this mode. ? write (synchronous ? one clock edge): on the write active-clock edge, the write data are written into the sram at the write address when wen is high. the setup time of the write address, write enables, and write data are minimal with respect to the write clock. write and read transfers are described with timing requirements beginning in "timing characteristics" on page 2-85 . enhancing seu performance sram structures are inherently susceptible to upsets caused by high-energy particles encountered in space. high-energy particles can cause an sram cell to change state, resulting in the loss or corruption of a valuable data bit. to allow users to achieve high levels of seu performance, actel has developed an intellectual property (ip) core to enhance the seu tolerance of the embedded sram within rtax-s/sl. this ip employs two upset -mitigation techniques: ? error detection and correction (edac) ? a background memory-refresher, or scrubber the edac ip employs the use of shortened hamming codes to provide the user with single-error correction/ double-error detection (sec /ded) capabilities. these shortened hamming codes provide the user with an implementation that has a reduced number of logic levels and less complexity than traditional hamming codes. the smartgen-generat ed edac ip supports ram widths of 8, 16, and 32 bits, with a variable ram depth from 256 to 4k words. the memory scrubber circui try has also been embedded in the edac ip as an opt ional block. the scrubber circuitry periodically refreshes memory in the background to ensure that no corruption of its contents has taken place while the memory was not in use. the refresh rate can be set by the user. the use of edac ip comb ined with the embedded memory scrubber circuitry, gives the rtax-s/sl an seu radiation performance level of better than 10 -10 errors/ bit-day. see the application note using edac ram for radtolerant rtax-s/sl fpgas and axcelerator fpgas .
rtax-s/sl radtolerant fpgas 2-84 v5.4 timing model and waveforms table 2-87 ? sram model figure 2-49 ? ram write timing waveforms figure 2-50 ? ram read timing waveforms wd rd ra ren wa wclk rclk wen wclk t w c kp t wxx s u t wxxhd t w c kh t w c kl wa< 11 :0>, wd<35:0>, wen<4:0> rclk ra<11:0>, ren<4:0> rd <35:0> t rxxsu t rxxhd t rckp t rckh t rckl t rck2rd1 t rck2rd2
rtax-s/sl radtolerant fpgas v5.4 2-85 timing characteristics table 2-88 ? one ram block (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description ?1 speed std. speed units min. max. min. max. write mode t wdasu write data setup vs. wclk 1.45 1.70 ns t wdahd write data hold vs. wclk 0.30 0.35 ns t wadsu write address setup vs. wclk 1.45 1.70 ns t wadhd write address hold vs. wclk 0.00 0.00 ns t wensu write enable setup vs. wclk 1.45 1.70 ns t wenhd write enable hold vs. wclk 0.30 0.35 ns t wckh wclk minimum high pulse width 0.75 0.75 ns t wclkl wclk minimum low pulse width 0.88 0.88 ns t wckp wclk minimum period 1.63 1.63 ns read mode t radsu read address setup vs. rclk 1.08 1.27 ns t radhd read address hold vs. rclk 0.00 0.00 ns t rensu read enable setup vs. rclk 1.08 1.27 ns t renhd read enable hold vs. rclk 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 1.77 2.08 ns t rck2rd2 rclk-to-out (non-pipelined) 2.90 3.41 ns t rclkh rclk minimum high pulse width 0.77 0.77 ns t rclkl rclk minimum low pulse width 0.93 0.93 ns t rckp rclk minimum period 1.70 1.70 ns note: timing data for this single block ram has a depth of 4,096 . for all other combinations, use actel's smarttime tool.
rtax-s/sl radtolerant fpgas 2-86 v5.4 table 2-89 ? two ram blocks are cascaded (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. write mode t wdasu write data setup vs. wclk 1.86 2.19 ns t wdahd write data hold vs. wclk 0.00 0.00 ns t wadsu write address setup vs. wclk 1.86 2.19 ns t wadhd write address hold vs. wclk 0.00 0.00 ns t wensu write enable setup vs. wclk 1.86 2.19 ns t wenhd write enable hold vs. wclk 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 ns t wclkl wclk minimum low pulse width 1.76 1.76 ns t wckp wclk minimum period 2.51 2.51 ns read mode t radsu read address setup vs. rclk 2.28 2.68 ns t radhd read address hold vs. rclk 0.00 0.00 ns t rensu read enable setup vs. rclk 2.28 2.68 ns t renhd read enable hold vs. rclk 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 1.92 2.26 ns t rck2rd2 rclk-to-out (non-pipelined) 3.03 3.56 ns t rclkh rclk minimum high pulse width 0.73 0.73 ns t rclkl rclk minimum low pulse width 1.89 1.89 ns t rckp rclk minimum period 2.62 2.62 ns note: timing data for two cascaded ram blocks uses a depth of 8, 192. for all other combinations , use actel's smarttime tool.
rtax-s/sl radtolerant fpgas v5.4 2-87 table 2-90 ? four ram blocks are cascaded (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. write mode t wdasu write data setup vs. wclk 3.17 3.73 ns t wdahd write data hold vs. wclk 0.00 0.00 ns t wadsu write address setup vs. wclk 3.17 3.73 ns t wadhd write address hold vs. wclk 0.00 0.00 ns t wensu write enable setup vs. wclk 3.17 3.73 ns t wenhd write enable hold vs. wclk 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 ns t wclkl wclk minimum low pulse width 2.51 2.51 ns t wckp wclk minimum period 3.26 3.26 ns read mode t radsu read address setup vs. rclk 4.13 4.85 ns t radhd read address hold vs. rclk 0.00 0.00 ns t rensu read enable setup vs. rclk 4.13 4.85 ns t renhd read enable hold vs. rclk 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 3.16 3.72 ns t rck2rd2 rclk-to-out (non-pipelined) 3.79 4.46 ns t rclkh rclk minimum high pulse width 0.73 0.73 ns t rclkl rclk minimum low pulse width 2.96 2.96 ns t rckp rclk minimum period 3.69 3.69 ns note: timing data for four cascaded ram blocks uses a depth of 16,384. for all other combinations, use actel's smarttime tool.
rtax-s/sl radtolerant fpgas 2-88 v5.4 table 2-91 ? eight ram blocks are cascaded (w orst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. write mode t wdasu write data setup vs. wclk 7.74 9.09 ns t wdahd write data hold vs. wclk 0.00 0.00 ns t wadsu write address setup vs. wclk 7.74 9.09 ns t wadhd write address hold vs. wclk 0.00 0.00 ns t wensu write enable setup vs. wclk 7.74 9.09 ns t wenhd write enable hold vs. wclk 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 ns t wclkl wclk minimum low pulse width 5.13 5.13 ns t wckp wclk minimum period 5.88 5.88 ns read mode t radsu read address setup vs. rclk 9.04 10.63 ns t radhd read address hold vs. rclk 0.00 0.00 ns t rensu read enable setup vs. rclk 9.04 10.63 ns t renhd read enable hold vs. rclk 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 4.54 5.33 ns t rck2rd2 rclk-to-out (non-pipelined) 6.60 7.76 ns t rclkh rclk minimum high pulse width 0.73 0.73 ns t rclkl rclk minimum low pulse width 5.77 5.77 ns t rckp rclk minimum period 6.50 6.50 ns note: timing data for eight cascaded ram blocks uses a depth of 32,768. for all other combinations, use actel's smarttime tool.
rtax-s/sl radtolerant fpgas v5.4 2-89 table 2-92 ? sixteen ram blocks are cascaded (w orst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. write mode t wdasu write data setup vs. wclk 22.14 26.03 ns t wdahd write data hold vs. wclk 0.30 0.35 ns t wadsu write address setup vs. wclk 22.14 26.03 ns t wadhd write address hold vs. wclk 0.30 0.35 ns t wensu write enable setup vs. wclk 22.14 26.03 ns t wenhd write enable hold vs. wclk 0.30 0.35 ns t wckh wclk minimum high pulse width 1.31 1.54 ns t wclkl wclk minimum low pulse width 23.34 27.44 ns t wckp wclk minimum period 46.69 54.88 ns read mode t radsu read address setup vs. rclk 24.27 28.53 ns t radhd read address hold vs. rclk 0.00 0.00 ns t rensu read enable setup vs. rclk 24.27 28.53 ns t renhd read enable hold vs. rclk 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 17.02 20.01 ns t rck2rd2 rclk-to-out (non-pipelined) 18.62 21.89 ns t rclkh rclk minimum high pulse width 1.27 1.49 ns t rclkl rclk minimum low pulse width 25.10 29.51 ns t rckp rclk minimum period 50.21 59.02 ns note: timing data for sixteen cascaded ram blocks uses a depth of 65,536. for all other combinations, use actel's smarttime tool.
rtax-s/sl radtolerant fpgas 2-90 v5.4 fifo every memory block has its own embedded fifo controller. each fifo block has one read port and one write port. this embedded fifo controller uses no internal fpga logic and features: ? glitch-free fifo flags ? gray-code address counters/pointers to prevent metastability problems ? overflow and underflow control both ports are configurable in various size from 4kx1 to 128x36, similar to the ram block size. each port is fully synchronous. read and write operatio ns can be completely independent. data on the appropriate wd pins are written to the fifo on every active wclk edge as long as wen is high. data is read from the fifo and output on the appropriate rd pins on every active rclk edge as long as ren is asserted. the fifo block offers programmable almost-empty (aempty) and almost-full (afull) flags as well as empty and full flags ( figure 2-51 ): ? the full flag is synchronous to wclk. it allows the fifo to inhibi t writing when full. ? the empty flag is synchronous to rclk. it allows the fifo to inhibit reading at the empty condition. note: actel recommends that the wclk and the rclk are in phase with each other. for more information refer to the application note, empty and full flag behaviors of the axcelerator fifo controller . gray code counters are used to prevent metastability problems associated with flag logic. the depth of the fifo is dependent on the data width and the number of memory blocks used to create the fifo. the write operations to the fifo are synchronous with respect to the wclk, and the read oper ations are synchronous with respect to the rclk. the fifo block may be reset to the empty state the fifo control unit was not implemented with seu- hardened registers. designs requiring high seu tolerance should implement the fifo control unit from hardened core logic. figure 2-51 ? rtax-s/sl ram with embedded fifo controller cnt 16 e cnt 16 e = = afval aeval > > = sub 16 rclk wd wclk clr fwen fren depth[3:0] rd [n-1:0] wd [n-1:0] rclk wclk ra [j:0] wa [j:0] ren wen full aempty afull empty rd pipe rw[2:0] ww[2:0] width[2:0] ram
rtax-s/sl radtolerant fpgas v5.4 2-91 fifo flag logic the fifo is user configurab le into various depths and widths. figure 2-52 shows the fifo address counter details. ? bits 11 to 5 are active for all modes. ? as the data word size is reduced, more least- significant bits are added to the address. ? as the number of cascad ed blocks increases, the number of significant bits in the address increases. for example, if four blocks are cascaded as a 1kx16 fifo with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each ram block, whereas bits 13 an d 12 will be used to specify the ram block. the afull and aempty flag threshold values are programmable. the threshol d values are afval and aeval, respectively. although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. note that the effective number of threshold bits corresponds to the range of active bits in the fifo address space ( table 2-93 ). note: inactive counter bits are set to zero. figure 2-52 ? fifo address counters table 2-93 ? fifo flag logic mode inactive aeval/afval bits inactive diff bits (set to 0) diff comparison to afval/aeval non-cascade [7:4] [15:12] diff[11:8] withae/fval[3:0] cascade 2 blocks [7:5] [15:13] diff[12:8] withae/fval[4:0] cascade 4 blocks [7:6] [15:14] diff[13:8] withae/fval[5:0] cascade 8 blocks [7] [15] diff[14:8] withae/fval[6:0] cascade 16 blocks none none diff[15:8] withae/fval[7:0] cntr [12] activate fifo address counters >> ren [4:0], rad [11:0] >> wen [4:0], wad [11:0] [12:w] [13:w] [14:w] [15:w] 128x36 1kx4 512x9 256x18 [11:5] [11:4] [11:3] [11:2] [11:1] [11:0] 4kx1 2kx2 variable active address space cntr [15] activate cntr [2] activate cntr [3] activate cntr [4] activate cntr [11:5] always active cntr [13] activate cntr [14] activate cntr [0] activate cntr [1] activate cas 16 blks by 1 by 2 by 4 by 9 by 18 by 36 cas 2 blks cas 4 blks cas 8 blks mode when active counter bits r/w en[3] r/w add[0] r/w add[1] r/w add[2] r/w add[3] r/w add[7:5] r/w add[11:8] r/w en[0] r/w en[1] r/w en[2] r/w add[4] fifo address aeval/afval[7] not compared not compared not compared not compared not compared not compared aeval/afval[3:0] aeval/afval[4] aeval/afval[5] aeval/afval[6] cntr [15:0] alignment of threshold bits
rtax-s/sl radtolerant fpgas 2-92 v5.4 figure 2-53 illustrates flag generation. the veril og statements for fl ag assignment are: assign af = (diff[15:0] >={afval[7:0],8'b00000000})?1:0; assign ae = ({aeval[7:0],8'b00000000}>=diff[15:0])?1:0; the number of diff-bits active depends on the configuration depth and width ( table 2-94 ). the active-high clr pin is used to reset the fifo to the empty state, which sets full and afull low, and empty and aempty high. assuming that the empty flag is not set, new data is read from the fifo when ren is valid on the active edge of the clock. write and read transfers are de scribed with timing requirements in "timing characteristics" on page 2-95 . for more information refer to the application note, empty and full flag behaviors of the axcelerator fifo controller . figure 2-53 ? almost-empty and almost-full logic table 2-94 ? number of available configuration bits number of blocks block dxw number of aeval/afval bits 11x14 21x24 22x15 41x44 42x25 44x16 81x84 82x45 84x26 88x17 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 wcntr [15:0] wclk rcntr [15:0] rclk 16 16 x y x y aempty afull x>=y (16-bit) diff [15:0] aeval [7:0], gnd [7:0] (msb....lsb) afval [7:0], gnd [7:0] (msb....lsb)
rtax-s/sl radtolerant fpgas v5.4 2-93 glitch elimination an analog filter is adde d to each fifo controller to guarantee, glitch-f ree fifo-flag logic. overflow and un derflow control the counter msb keeps track of the difference between the read address (ra) and the write address (wa). the empty flag is set when the read and write addresses are equal. to prevent underflow, the write address is double- sampled by the read clock prior to comparison with the read address (part a in figure 2-54 ). to prevent overflow, the read address is double-s ampled by the write clock prior to comparison to th e write address (part b in figure 2-54 ). fifo configurations unlike the ram, the fifo's write width and read width cannot be specified independently. for the fifo, the write and read widths must be the same. the width pins are used to specify one of six allowable word widths, as shown in table 2-95 . the depth pins allow ram cells to be cascaded to create larger fifos. the four pins a llow depths of 2, 4, 8, and 16 to be specified. table 2-84 on page 2-81 describes the fifo depth options for various data width and memory blocks. interface figure 2-55 shows a logic block diagram of the rtax-s/sl fifo module. cascading fifo blocks fifo blocks can be cascaded to create deeper fifo functions. when building larger fifo blocks, if the word width can be fractured in a multi-bit fifo, the fractured word configuration is re commended over a cascaded configuration. for example, 256x36 can be configured as two blocks of 256x18. this sh ould be taken into account when building the fifo blocks manually. however, when using smartgen, the user only needs to specify the depth and width of the necessary fifo blocks. smartgen automatically configures these blocks to optimize performance. clock as with ram configuration, the rclk and wclk pins have independent polarity selection figure 2-54 ? overflow and underflow control ab = empty wa ra rclk = full ra wa wclk table 2-95 ? fifo width configurations width(2:0) wxd 000 1x4k 001 2x2k 010 4x1k 011 9x512 100 18x256 101 36x128 11x reserved figure 2-55 ? fifo block diagram depth [3:0] rd [35:0] full empty afull aempty width [2:0] fwen fren pipe rclk wd [35:0] aeval [7:0] afval [7:0] wclk clr
rtax-s/sl radtolerant fpgas 2-94 v5.4 table 2-96 ? fifo signal description signal direction description wclk input write clock (active either edge). fwen input fifo write enable . when this signal is asserted, th e wd bus data is latched into the fifo, and the internal write counters are incremented. wd[n-1:0] input write data bus. the value n is de pendent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. full output active high signal indicating that the fifo is full. when this signal is set, additional write requests are ignored. afull output active high signal indicating that the fifo is afull. afval input 8-bit input defining the afull value of the fifo. rclk input read clock (a ctive either edge). fren input fifo read enable. rd[n-1:0] output read data bus. the value n is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. empty output empty flag indicating that the fi fo is empty. when this signal is asserted, attempts to read the fifo will be ignored. aempty output active high signal indicating that the fifo is aempty. aeval input 8-bit input defining the almost-empty value of the fifo. pipe input sets the pipe option on or off. clr input active high clear input. depth input determines the depth of the fifo and the number of fifos to be cascaded. width input determines the width of the dataword / width of the fifo, and the number of the fifos to be cascaded.
rtax-s/sl radtolerant fpgas v5.4 2-95 timing characteristics figure 2-56 ? fifo model figure 2-57 ? fifo write timing wd fwen fren rclk wclk rd afull empty aempty full clr t wckp t wsu t whd t wck2xf t clr2xf t clr2hf t wckh t wckl wclk clr wd<35:0>, fwen empty, aempty, afull, full
rtax-s/sl radtolerant fpgas 2-96 v5.4 figure 2-58 ? fifo read timing rclk clr t rckp t rsu t rhd t rck2rd1 t rck2rd2 t ck2xf t clr2xf t clrhf t rckh t rckl fren empty, aempty, afull, full rd <35:0>
rtax-s/sl radtolerant fpgas v5.4 2-97 table 2-97 ? one fifo block (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. fifo module timing t wsu write setup 15.26 17.93 ns t whd write hold 0.30 0.35 ns t wckh wclk high 0.75 0.75 ns t wckl wclk low 0.88 0.88 ns t wckp minimum wclk period 1.63 1.63 t rsu read setup 15.58 18.31 ns t rhd read hold 0.00 0.00 ns t rckh rclk high 0.77 0.77 ns t rckl rclk low 0.93 0.93 ns t rckp minimum rclk period 1.70 1.70 t clr2ff clear-to-flag (empty/full) 2.57 3.02 ns t clr2af clear-to-flag (aempty/afull) 5.88 6.91 ns t ck2ff clock-to-flag (empty/full) 2.85 3.35 ns t ck2af clock-to-flag (aempty/afull) 6.75 7.94 ns t rck2rd1 rclk-to-out (pipelined) 1.77 2.08 ns t rck2rd2 rclk-to-out (non-pipelined) 3.50 4.12 ns note: timing data for this single cascaded fifo block uses a depth of 4,096. for all other combinations, please use actel's timing software. table 2-98 ? two fifo blocks are cascaded (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. fifo module timing t wsu write setup 18.40 21.64 ns t whd write hold 0.00 0.00 ns t wckh wclk high 0.75 0.75 ns t wckl wclk low 1.76 1.76 ns t wckp minimum wclk period 2.51 2.51 t rsu read setup 19.18 22.55 ns t rhd read hold 0.00 0.00 ns t rckh rclk high 0.73 0.73 ns t rckl rclk low 1.89 1.89 ns t rckp minimum rclk period 2.62 2.62 t clr2ff clear-to-flag (empty/full) 2.57 3.02 ns t clr2af clear-to-flag (aempty/afull) 5.88 6.91 ns t ck2ff clock-to-flag (empty/full) 2.85 3.35 ns t ck2af clock-to-flag (aempty/afull) 6.75 7.94 ns t rck2rd1 rclk-to-out (pipelined) 1.92 2.26 ns t rck2rd2 rclk-to-out (non-pipelined) 3.03 3.56 ns note: timing data for two cascaded fifo blocks uses a depth of 8,19 2. for all other combinations, pl ease use actel's timing software.
rtax-s/sl radtolerant fpgas 2-98 v5.4 table 2-99 ? four fifo blocks are cascaded (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. fifo module timing t wsu write setup 19.55 22.98 ns t whd write hold 0.00 0.00 ns t wckh wclk high 0.75 0.75 ns t wckl wclk low 2.51 2.51 ns t wckp minimum wclk period 3.26 3.26 t rsu read setup 20.44 24.03 ns t rhd read hold 0.00 0.00 ns t rckh rclk high 0.73 0.73 ns t rckl rclk low 2.96 2.96 ns t rckp minimum rclk period 3.69 3.69 t clr2ff clear-to-flag (empty /full) 2.57 3.02 ns t clr2af clear-to-flag (aempt y/afull) 5.88 6.91 ns t ck2ff clock-to-flag (empty/full) 2.85 3.35 ns t ck2af clock-to-flag (aempty/afull) 6.75 7.94 ns t rck2rd1 rclk-to-out (pipelined) 3.16 3.72 ns t rck2rd2 rclk-to-out (non-pipelined) 3.79 4.46 ns note: timing data for four cascaded fifo blocks uses a depth of 16,384. for all other comb inations, please use actel's timing softwar e. table 2-100 ? eight fifo blocks are cascaded (w orst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter '?1' speed 'std' speed units description min. max. min. max. fifo module timing t wsu write setup 20.69 24.32 ns t whd write hold 0.00 0.00 ns t wckh wclk high 0.75 0.75 ns t wckl wclk low 5.13 5.13 ns t wckp minimum wclk period 5.88 5.88 t rsu read setup 21.71 25.52 ns t rhd read hold 0.00 0.00 ns t rckh rclk high 0.73 0.73 ns t rckl rclk low 5.77 5.77 ns t rckp minimum rclk period 6.50 6.50 t clr2ff clear-to-flag (empty/full) 2.57 3.02 ns t clr2af clear-to-flag (aempty/afull) 5.88 6.91 ns t ck2ff clock-to-flag (em pty/full) 2.85 3.35 ns t ck2af clock-to-flag (aempty/afull) 6.75 7.94 ns t rck2rd1 rclk-to-out (pipelined) 4.54 5.33 ns t rck2rd2 rclk-to-out (non-pipelined) 6.60 7.76 ns note: timing data for eight cascaded fifo blocks uses a depth of 32,76 8. for all other combinations, pl ease use actel's timing softwa re.
rtax-s/sl radtolerant fpgas v5.4 2-99 building ram and fifo modules ram and fifo modules can be generated and included in a design in two different ways: ? using the smartgen core generator where the user defines the depth and width of the fifo/ram, and then instantiates this block into the design (please refer to the actel smartgen, flashrom, analog system builder, and flash memory system builder user?s guide for more information). ? the alternative is to instantiate th e ram/fifo blocks manually, using inverters for polarity control and tying all unused data bits to ground. table 2-101 ? sixteen fifo blocks are cascaded (worst-case military conditions v cca = 1.4 v, v cci = 3.0 v, t j = 125c) parameter description '?1' speed 'std' speed units min. max. min. max. fifo module timing t wsu write setup 21.85 25.69 ns t whd write hold 0.00 0.00 ns t wckh wclk high 0.75 0.75 ns t wckl wclk low 13.40 13.40 ns t wckp minimum wclk period 14.15 14.15 t rsu read setup 22.97 27.00 ns t rhd read hold 0.00 0.00 ns t rckh rclk high 0.73 0.73 ns t rckl rclk low 14.41 14.41 ns t rckp minimum rclk period 15.14 15.14 t clr2ff clear-to-flag (empty/full) 2.57 3.02 ns t clr2af clear-to-flag (aempty/afull) 5.88 6.91 ns t ck2ff clock-to-flag (empty/full) 2.85 3.35 ns t ck2af clock-to-flag (aempty/afull) 6.75 7.94 ns t rck2rd1 rclk-to-out (pipelined) 16.17 19.01 ns t rck2rd2 rclk-to-out (non-pipelined) 17.18 20.19 ns note: timing data for sixteen cascaded fifo bl ocks uses a depth of 65,536. for all othe r combinations, please use actel's timing software.
rtax-s/sl radtolerant fpgas 2-100 v5.4 other architectural features charge pump bypass to reduce power consumption, the internal charge pump can be bypassed and an exte rnal power supply voltage can be used instead. this sa ves the internal charge-pump operating current, resulting in no dc current draw. the rtax-s/sl family devices have a dedicated "v pump " pin that can be used to access an external charge pump device. in normal chip operation, when using the internal charge pump, v pump should be tied to gnd. when the voltage level on v pump is set to 3.3 v, the internal charge pump is turned off, and the v pump voltage will be used as the charge pump voltage. adequate voltage regulation ( i.e., high drive, low output impedance, and good decoupling) should be used at v pump . jtag rtax-s/sl offers a jtag interface that is compliant with the ieee 1149.1 standard except for the device id length which is 33 bits. the user ca n employ the jtag interface for probing a design and executing any jtag public instructions as defined in the table 2-102 . the jtag pins and probes are configured as a lvttl standard port. refer to the ieee standard 1149.1 (jtag) in the axcelerator family application note, which also applies to the rtax-s/sl family of devices. the jtag pins should not be left floating on flight systems. interface the interface consists of f our inputs: test mode select (tms), test data in (tdi), test clock (tck), tap controller reset (trst), and an output, test data out (tdo). tms, tdi, and trst have on-ch ip pull-up resistors. trst trst (test-logic reset) is an active-low asynchronous reset signal to the tap controller. the trst input can be used to reset the test access port (tap) controller to the trst state. the tap controller can be held at this state permanently by grounding the trst pin. to hold the jtag tap controller in the trst state, it is recommended to connect trst directly to ground for flight. there is an optional internal pull-up resistor available for the trst input that can be set by the user at programming. care should be exercised when using this option in combination with an external tie-off to ground. an on-chip power-on-reset (powrst) circuit is included. powrst has the same function as "trst," but it only occurs at power-up or during recovery from a v cca and/ or v ccda voltage drop. tdo tdo is normally tristated, and it is active only when the tap controller is in the "shi ft_dr" state or "shift_ir" state. the least significant bit of the selected register (i.e., ir or dr) is clocked ou t to tdo first by the falling edge of tck. tap controller the tap controller is complia nt with the ieee standard 1149.1. it is a state machine of 16 states that controls the instruction register (ir) and the data registers (such as boundary-scan register, idcode, usrcode, bypass, etc.). the tap controller st eps into one of the states depending on the sequence of tms at the rising edges of tck. instruction register (ir) the ir has five bits (ir4 to ir0). at the trst state, ir is reset to idcode. each time when ir is selected, it goes through "select ir-scan," "cap ture-ir," "shift-ir," all the way through "update-ir." when there is no test error, the first five data bits coming out of tdo during the "shift-ir" will be "10111." if a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "tdo_errorb," "proba_errorb," and "probb_errorb." the error(s) will be erased when the tap is at the "update-ir" or the trst state. when in user m ode start-up sequence, if the micro-probe has not been used, the "proba_errorb" is used as a "power-up do ne successfully" flag. during flight, the following co nfigurations for all jtag and probe pins are recommended ( table 2-103 on page 2-101 ). table 2-102 ? jtag instruction code instruction (ir4:ir0) binary code extest 00000 preload / sample 00001 intest 00010 usercode 00011 idcode 00100 highz 01110 clamp 01111 diagnostic 10000 reserved all others bypass 11111
rtax-s/sl radtolerant fpgas v5.4 2-101 data registers (drs) data registers are distributed throughout the chip. they store testing/programming vectors. the msb of a data register is connected to td i, while the lsb is connected to tdo. there are different types of data registers. descriptions of the main registers are as follow: 1. idcode: the idcode is a 33-bit hard coded jtag silicon signature. it is a hardwired device id code, which contains the actel identity , part number, and version number in a specific jtag format. refer to the ieee standard 1149.1 (jtag) in the axcelerator family application note fo r more information. 2. usercode: the usercode is a 33-bit programmable jtag silicon signature. it is a suppleme ntary identity code for the user to program information to distinguish different programmed parts. userco de fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. refer to the ieee standard 1149.1 (jtag) in the axcelerator family application note for more information. 3. boundary-scan register (bsr): each i/o contains three bsr cells. each cell has a shift register bit, a latch, and two muxes. the boundary- scan cells are used for th e output-enable (e), output (o), and input (i) registers. the bit order of the boundary-scan cells for each of them is e-o-i. the boundary-scan cells are then chained serially to form the bsr. the length of the bsr is the number of i/os in the die (not the package) multiplied by three. this excludes special function pins (trst, tck, tms, tdi, tdo, pra, prb, prc, prd, and vpump). 4. bypass register (byr): this is the "1-bit" register. it is used to shorten the tdi-tdo serial chain in board-level testing to only one bit per device not being tested. it is also selected for all "reserved" or unused instructions. probing internal activities of the jtag interface can be observed via the silicon explorer ii probes: "pra," "prb," "prc," and "prd." special fuses security actel antifuse fpgas, with fuselock technology, offer the highest level of design security available in a programmable logic device. since antifuse fpgas are live at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the de vice during power-up, thus making device cloning impossible. in addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. both invasive and noninvasive attacks against an rtax-s/ sl device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the design security in nonvolatile flash and antifuse fpgas white paper). look for this symbol to ensure your valuable ip is secure. table 2-103 ? jtag and probe pin recommendations for flight jtag and probe pins configurations tck ? can be hardwired to v ccda or ground ? can be driven to v ccda or ground ? must not be left unterminated tdo must be left unconnected tdi ? can be hardwired or driven to v ccda ? can be left unconnected (equipped with internal 10 k pull-up resistor) tms ? can be hardwired or driven to v ccda ? can be left unconnected (equipped with internal 10 k pull-up resistor) trst must be hardwired to ground (equipped with optional internal 10 k pull-up resistor) pra/b/c/d must be left unconnected figure 2-59 ? fuselock logo ? e u
rtax-s/sl radtolerant fpgas 2-102 v5.4 to ensure maximum security in rtax-s/sl devices, it is recommended that the user program the device security fuse (sfus). when programme d, the silicon explorer ii testing probes are disabled to prevent internal probing, and the programming interface is also disabled. all jtag public instructions are st ill accessible by the user. for more information, refer to actel?s implementation of security in actel antifuse fpgas application note. global set fuse the global set fuse determ ines if all r-cells and i/o registers (inreg, outreg, an d enreg) are either cleared or preset by driving the gc lr and gpset inputs of all r-cells and i/o registers ( "r-cell" on page 2-66 ). default setting is to clear all registers (gclr = 0 and gpset =1) at device power-up. when the gbsetfus option is checked during fuse file generation, all registers are preset (gclr = 1 and gpset= 0). a local clr or preset will take precedence overt this settin g. both pins are pulled high during normal device operation. for use details, see libero ide online help. silicon explorer ii probe interface silicon explorer ii is an integrated hardware and software solution that, in conjunction with the designer tools, allows users to exam ine any of the internal nets (except i/o registers) of the device while it is operating in a prototype or a production system. the user can probe up to four nodes at a time without changing the placement and routing of th e design and without using any additional device resources. highlighted nets in designer?s chipplanner can be accessed using silicon explorer ii in order to observe their real time values. silicon explorer ii's noninvas ive method does not alter timing or loading effects, thus shortening the debug cycle. in addition, silicon explorer ii does not require relayout or additional muxes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. by eliminating multiple place-a nd-route program cycles the integrity of the design is maintained throughout the debug process. each member of the rtax-s/sl family has four external pads: pra, prb, prc, and prd. these can be used to bring out four probe signals from the rtax-s/sl device. each core tile can has up to two probe signals. to disallow probing, the sfus security fu se in the silicon signature has to be programmed (see "special fuses" on page 2- 101 for more information). silicon explorer ii connects to the host pc using a standard serial port connector. connections to the circuit board are achieved using a nine-pin d-sub connector ( figure 1-9 on page 1-8 ). once the design has been placed-and-routed, and the rtax-s/sl device has been programmed, silicon explorer ii can be connected and the explorer software can be launched. silicon explorer ii comes with an additional optional pc hosted tool that emulates an 18-channel logic analyzer. four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. the software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. programming device programming is supp orted through the silicon sculptor 3, a single-site, robust and compact device programmer for the pc. up to four s ilicon sculptor 3s can be daisy-chained and controlled from a single pc host. with standalone software for the pc, silicon sculptor 3 is designed to allow concurrent programming of multiple units from the same pc when daisy-chained. silicon sculptor 3 programs devices independently to achieve the fastest programming times possible. each fuse is verified by silicon sculptor 3 to ensure correct programming. furthermore, at the end of programming, there are integrity tests th at are run to ensure that programming was completed properly. not only does it test programmed and nonprogrammed fuses, silicon sculptor 3 also provides a self-test to test its own hardware extensively. programming an rtax-s/sl device using silicon sculptor 3 is similar to programming any other antifuse device. the procedure is as follows: 1. load the afm file. 2. select the device to be programmed. 3. begin programming. when the design is ready to go to production, actel offers device volume-programming services either through distribution partners or via our in-house programming center. for more details on programming the rtax-s/sl devices, please refer to the silicon sculptor user?s guide .
rtax-s/sl radtolerant fpgas v5.4 3-1 package pin assignments 208-pin cqfp note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . figure 3-1 ? 208-pin cqfp (top view) ceramic tie bar 208-pin cqfp 1 2 3 4 49 50 51 52 53 54 55 56 101 102 103 104 156 155 154 153 108 107 106 105 208 207 206 205 160 159 158 157 pin 1
rtax-s/sl radtolerant fpgas 3-2 v5.4 208 cqfp rtax250s/sl function pin number bank 0 io02nb0f0 197 io03nb0f0 198 io03pb0f0 199 io12nb0f0/hclkan 191 io12pb0f0/hclkap 192 io13nb0f0/hclkbn 185 io13pb0f0/hclkbp 186 bank 1 io14nb1f1/hclkcn 180 io14pb1f1/hclkcp 181 io15nb1f1/hclkdn 174 io15pb1f1/hclkdp 175 io16nb1f1 170 io16pb1f1 171 io24nb1f1 165 io24pb1f1 166 io26nb1f1 161 io26pb1f1 162 io27nb1f1 159 io27pb1f1 160 bank 2 io29nb2f2 151 io29pb2f2 153 io30nb2f2 152 io30pb2f2 154 io31pb2f2 148 io32nb2f2 146 io32pb2f2 147 io34nb2f2 144 io34pb2f2 145 io39nb2f2 139 io39pb2f2 140 io40pb2f2 141 io41nb2f2 137 io41pb2f2 138 io43nb2f2 132 io43pb2f2 134 io44nb2f2 131 io44pb2f2 133 bank 3 io45nb3f3 127 io45pb3f3 129 io46nb3f3 126 io46pb3f3 128 io48nb3f3 122 io48pb3f3 123 io50nb3f3 120 io50pb3f3 121 io55nb3f3 116 io55pb3f3 117 io57nb3f3 114 io57pb3f3 115 io59nb3f3 110 io59pb3f3 111 io60nb3f3 108 io60pb3f3 109 io61nb3f3 106 io61pb3f3 107 bank 4 io62nb4f4 100 io62pb4f4 103 io63nb4f4 101 io63pb4f4 102 io64nb4f4 96 io64pb4f4 97 io72nb4f4 91 io72pb4f4 92 io74nb4f4/clken 87 io74pb4f4/clkep 88 io75nb4f4/clkfn 81 io75pb4f4/clkfp 82 bank 5 io76nb5f5/clkgn 76 208 cqfp rtax250s/sl function pin number io76pb5f5/clkgp 77 io77nb5f5/clkhn 70 io77pb5f5/clkhp 71 io78nb5f5 66 io78pb5f5 67 io86nb5f5 62 io87nb5f5 60 io87pb5f5 61 io88nb5f5 56 io88pb5f5 57 io89nb5f5 54 io89pb5f5 55 bank 6 io91nb6f6 47 io91pb6f6 49 io92nb6f6 48 io92pb6f6 50 io93nb6f6 42 io93pb6f6 43 io94pb6f6 44 io96nb6f6 40 io96pb6f6 41 io101nb6f6 35 io101pb6f6 36 io102pb6f6 37 io103nb6f6 33 io103pb6f6 34 io105nb6f6 28 io105pb6f6 30 io106nb6f6 27 io106pb6f6 29 bank 7 io107nb7f7 23 io107pb7f7 25 io108nb7f7 22 io108pb7f7 24 io110nb7f7 18 208 cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-3 io110pb7f7 19 io112nb7f7 16 io112pb7f7 17 io117nb7f7 12 io117pb7f7 13 io119nb7f7 10 io119pb7f7 11 io121pb7f7 7 io122nb7f7 5 io122pb7f7 6 io123nb7f7 3 io123pb7f7 4 dedicated i/o gnd 9 gnd 15 gnd 21 gnd 32 gnd 39 gnd 46 gnd 51 gnd 59 gnd 65 gnd 69 gnd 90 gnd 94 gnd 99 gnd 104 gnd 113 gnd 119 gnd 125 gnd 136 gnd 143 gnd 150 gnd 155 gnd 164 gnd 169 gnd 173 208 cqfp rtax250s/sl function pin number gnd 194 gnd 196 gnd 201 gnd 208 nc 72 nc 73 nc 74 nc 75 nc 83 nc 84 nc 85 nc 86 nc 176 nc 177 nc 178 nc 179 nc 187 nc 188 nc 189 nc 190 pra 184 prb 183 prc 80 prd 79 tck 205 tdi 204 tdo 203 tms 206 trst 207 v cca 2 v cca 14 v cca 38 v cca 52 v cca 64 v cca 93 v cca 118 v cca 142 208 cqfp rtax250s/sl function pin number v cca 156 v cca 168 v cca 195 v ccda 1 v ccda 26 v ccda 53 v ccda 63 v ccda 78 v ccda 95 v ccda 105 v ccda 130 v ccda 157 v ccda 167 v ccda 182 v ccda 202 v cci b0 193 v cci b0 200 v cci b1 163 v cci b1 172 v cci b2 135 v cci b2 149 v cci b3 112 v cci b3 124 v cci b4 89 v cci b4 98 v cci b5 58 v cci b5 68 v cci b6 31 v cci b6 45 v cci b7 8 v cci b7 20 v pump 158 208 cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas 3-4 v5.4 256-pin cqfp note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . figure 3-2 ? 256-pin cqfp (top view) ceramic tie bar 256-pin cqfp 1 2 3 4 61 62 63 64 65 66 67 68 125 126 127 128 192 191 190 189 132 131 130 129 256 255 254 253 196 195 194 193 pin 1
rtax-s/sl radtolerant fpgas v5.4 3-5 256-pin cqfp rtax2000s/sl function pin number bank 0 io01nb0f0 248 io01pb0f0 249 io04nb0f0 246 io04pb0f0 247 io05nb0f0 242 io05pb0f0 243 io08nb0f0 240 io08pb0f0 241 bank 0 io37nb0f3 234 io37pb0f3 235 io41nb0f3/hclkan 232 io41pb0f3/hclkap 233 io42nb0f3/hclkbn 228 io42pb0f3/hclkbp 229 bank 1 - io43nb1f4/hclkcn 220 io43pb1f4/hclkcp 221 io44nb1f4/hclkdn 216 io44pb1f4/hclkdp 217 bank 1 io65nb1f6 210 io65pb1f6 211 io69nb1f6 208 io69pb1f6 209 io70nb1f6 199 io71nb1f6 204 io71pb1f6 205 io73nb1f6 202 io73pb1f6 203 io74nb1f6 197 io74pb1f6 198 bank 2 io87nb2f8 187 io87pb2f8 188 io89pb2f8 186 bank 2 io107nb2f10 184 io107pb2f10 185 io110nb2f10 180 io110pb2f10 181 io111nb2f10 178 io111pb2f10 179 io112nb2f10 174 io112pb2f10 175 io113nb2f10 172 io113pb2f10 173 io114nb2f10 168 io114pb2f10 169 io115nb2f10 166 io115pb2f10 167 io117nb2f10 162 io117pb2f10 163 bank 3 io139nb3f13 158 io139pb3f13 159 io141nb3f13 154 io141pb3f13 155 io142nb3f13 152 io142pb3f13 153 io145nb3f13 148 io145pb3f13 149 io146nb3f13 146 io146pb3f13 147 io147nb3f13 140 io147pb3f13 141 io148nb3f13 142 io148pb3f13 143 io149nb3f13 136 io149pb3f13 137 bank 3 io165nb3f15 135 io167nb3f15 133 256-pin cqfp rtax2000s/sl function pin number io167pb3f15 134 bank 4 io181nb4f17 124 io181pb4f17 125 io182nb4f17 122 io182pb4f17 123 io183nb4f17 118 io183pb4f17 119 io184nb4f17 116 io184pb4f17 117 io190nb4f17 112 io190pb4f17 113 io192nb4f17 110 io192pb4f17 111 bank 4 io212nb4f19/clken 104 io212pb4f19/clkep 105 io213nb4f19/clkfn 100 io213pb4f19/clkfp 101 bank 5 io214nb5f20/clkgn 92 io214pb5f20/clkgp 93 io215nb5f20/clkhn 88 io215pb5f20/clkhp 89 bank 5 io236nb5f22 82 io236pb5f22 83 io238nb5f22 80 io238pb5f22 81 io240nb5f22 76 io240pb5f22 77 io242nb5f22 74 io242pb5f22 75 io243nb5f22 70 io243pb5f22 71 io244nb5f22 68 io244pb5f22 69 256-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-6 v5.4 bank 6 io257pb6f24 60 io258nb6f24 58 io258pb6f24 59 bank 6 io279nb6f26 56 io279pb6f26 57 io280nb6f26 52 io280pb6f26 53 io281nb6f26 50 io281pb6f26 51 io282nb6f26 46 io282pb6f26 47 io284nb6f26 44 io284pb6f26 45 io285nb6f26 40 io285pb6f26 41 io286nb6f26 38 io286pb6f26 39 io287nb6f26 34 io287pb6f26 35 bank 7 9 io310nb7f29 30 io310pb7f29 31 io311nb7f29 26 io311pb7f29 27 io312nb7f29 24 io312pb7f29 25 io315nb7f29 20 io315pb7f29 21 io316nb7f29 18 io316pb7f29 19 io317nb7f29 14 io317pb7f29 15 io318nb7f29 12 io318pb7f29 13 io320nb7f29 8 256-pin cqfp rtax2000s/sl function pin number io320pb7f29 9 bank 7 io341nb7f31 6 io341pb7f31 7 dedicated i/o gnd 1 gnd 5 gnd 11 gnd 17 gnd 23 gnd 29 gnd 33 gnd 37 gnd 43 gnd 49 gnd 55 gnd 62 gnd 64 gnd 65 gnd 73 gnd 79 gnd 85 gnd 91 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 128 gnd 129 gnd 132 gnd 139 gnd 145 gnd 151 gnd 157 gnd 161 gnd 165 256-pin cqfp rtax2000s/sl function pin number gnd 171 gnd 177 gnd 183 gnd 190 gnd 192 gnd 193 gnd 201 gnd 207 gnd 213 gnd 219 gnd 225 gnd 231 gnd 239 gnd 245 gnd 256 pra 227 prb 226 prc 99 prd 98 tck 253 tdi 252 tdo 250 tms 254 trst 255 v cca 3 v cca 4 v cca 22 v cca 42 v cca 61 v cca 63 v cca 84 v cca 108 v cca 127 v cca 131 v cca 150 v cca 170 v cca 189 256-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-7 v cca 191 v cca 212 v cca 238 v ccda 2 v ccda 32 v ccda 66 v ccda 67 v ccda 86 v ccda 87 v ccda 94 v ccda 95 v ccda 96 v ccda 106 v ccda 107 v ccda 126 v ccda 130 v ccda 160 v ccda 194 v ccda 196 v ccda 214 v ccda 215 v ccda 222 v ccda 223 v ccda 224 v ccda 236 v ccda 237 v ccda 251 v cci b0 230 v cci b0 244 v cci b1 200 v cci b1 206 v cci b1 218 v cci b2 164 v cci b2 176 v cci b2 182 v cci b3 138 v cci b3 144 256-pin cqfp rtax2000s/sl function pin number v cci b3 156 v cci b4 102 v cci b4 114 v cci b4 120 v cci b5 72 v cci b5 78 v cci b5 90 v cci b6 36 v cci b6 48 v cci b6 54 v cci b7 10 v cci b7 16 v cci b7 28 v pump 195 256-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-8 v5.4 352-pin cqfp note: the 352-pin cqfp pin assignments for rtax250s/sl, rtax 1000s/sl and rtax2000s/sl are co mpatible except for the following pins. figure 3-3 ? 352-pin cqfp table 3-1 ? compatibility table fo r the cq352 package rtax250s/sl rtax1000s/sl rtax2000s/sl rtax4000s/sl rtax250s/sl na 117, 148, 294, 327, 328, 91, 117, 130, 131, 148, 174, 268, 294, 307, 308, 327, 328, not pin compatible rtax1000s/sl 117, 148, 294, 327, 328, na 91,130, 131, 174, 268, 307, 308 not pin compatible rtax2000s/sl 91, 117, 130, 131, 148, 174, 268, 294, 307, 308, 327, 328, 91,130, 131, 174, 268, 307, 308 na not pin compatible ceramic tie bar 352-pin cqfp 1 2 3 4 41 42 43 44 45 46 47 48 49 85 86 87 88 89 90 91 92 127 128 129 130 131 132 133 134 135 173 174 175 176 264 263 262 261 180 179 178 177 223 222 221 220 219 218 217 216 215 352 351 350 349 339 338 337 336 335 334 333 332 331 268 267 266 265 pin 1
rtax-s/sl radtolerant fpgas v5.4 3-9 where exceptions occur, the smaller density devices have those pins designated as no connects (nc). customers are therefore recommended to layout th eir board targeting the larger density device, in order to preserve interchangeability between the two devices. note: rtax4000s is not pin compatible with any of the smaller density devices. for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx .
rtax-s/sl radtolerant fpgas 3-10 v5.4 352-pin cqfp rtax250s/sl function pin number bank 0 io00nb0f0 341 io00pb0f0 342 io01nb0f0 343 io02nb0f0 337 io02pb0f0 338 io04nb0f0 335 io04pb0f0 336 io06nb0f0 331 io06pb0f0 332 io08nb0f0 325 io08pb0f0 326 io10nb0f0 323 io10pb0f0 324 io12nb0f0/hclkan 319 io12pb0f0/hclkap 320 io13nb0f0/hclkbn 313 io13pb0f0/hclkbp 314 bank 1 io14nb1f1/hclkcn 305 io14pb1f1/hclkcp 306 io15nb1f1/hclkdn 299 io15pb1f1/hclkdp 300 io16nb1f1 289 io16pb1f1 290 io17nb1f1 295 io17pb1f1 296 io18nb1f1 287 io18pb1f1 288 io20nb1f1 283 io20pb1f1 284 io22nb1f1 277 io22pb1f1 278 io23nb1f1 281 io23pb1f1 282 io24nb1f1 275 io24pb1f1 276 io25nb1f1 271 io25pb1f1 272 io27nb1f1 269 io27pb1f1 270 bank 2 io29nb2f2 261 io29pb2f2 262 io30nb2f2 259 io30pb2f2 260 io31nb2f2 255 io31pb2f2 256 io33nb2f2 249 io33pb2f2 250 io34nb2f2 253 io34pb2f2 254 io35nb2f2 247 io35pb2f2 248 io36nb2f2 243 io36pb2f2 244 io37nb2f2 241 io37pb2f2 242 io38nb2f2 237 io38pb2f2 238 io39nb2f2 235 io39pb2f2 236 io41nb2f2 231 io41pb2f2 232 io42nb2f2 229 io42pb2f2 230 io43nb2f2 225 io43pb2f2 226 io44nb2f2 223 io44pb2f2 224 bank 3 io45nb3f3 217 io45pb3f3 218 io46nb3f3 219 352-pin cqfp rtax250s/sl function pin number io46pb3f3 220 io47nb3f3 213 io47pb3f3 214 io48nb3f3 211 io48pb3f3 212 io49nb3f3 207 io49pb3f3 208 io51nb3f3 205 io51pb3f3 206 io52nb3f3 201 io52pb3f3 202 io53nb3f3 199 io53pb3f3 200 io54nb3f3 195 io54pb3f3 196 io55nb3f3 193 io55pb3f3 194 io56nb3f3 187 io56pb3f3 188 io57nb3f3 189 io57pb3f3 190 io59nb3f3 183 io59pb3f3 184 io60nb3f3 181 io60pb3f3 182 io61nb3f3 179 io61pb3f3 180 bank 4 io62nb4f4 172 io62pb4f4 173 io64nb4f4 166 io64pb4f4 167 io65nb4f4 170 io65pb4f4 171 io66nb4f4 164 io66pb4f4 165 io67nb4f4 160 352-pin cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-11 io67pb4f4 161 io68nb4f4 158 io68pb4f4 159 io70nb4f4 154 io70pb4f4 155 io72nb4f4 152 io72pb4f4 153 io73nb4f4 146 io73pb4f4 147 io74nb4f4/clken 142 io74pb4f4/clkep 143 io75nb4f4/clkfn 136 io75pb4f4/clkfp 137 bank 5 io76nb5f5/clkgn 128 io76pb5f5/clkgp 129 io77nb5f5/clkhn 122 io77pb5f5/clkhp 123 io78nb5f5 112 io78pb5f5 113 io79nb5f5 118 io79pb5f5 119 io80nb5f5 110 io80pb5f5 111 io82nb5f5 106 io82pb5f5 107 io84nb5f5 100 io84pb5f5 101 io85nb5f5 104 io85pb5f5 105 io86nb5f5 98 io86pb5f5 99 io87nb5f5 94 io87pb5f5 95 io89nb5f5 92 io89pb5f5 93 bank 6 352-pin cqfp rtax250s/sl function pin number io90pb6f6 86 io91nb6f6 84 io91pb6f6 85 io92nb6f6 78 io92pb6f6 79 io93nb6f6 82 io93pb6f6 83 io95nb6f6 76 io95pb6f6 77 io96nb6f6 72 io96pb6f6 73 io97nb6f6 70 io97pb6f6 71 io98nb6f6 66 io98pb6f6 67 io99nb6f6 64 io99pb6f6 65 io100nb6f6 60 io100pb6f6 61 io101nb6f6 58 io101pb6f6 59 io103nb6f6 54 io103pb6f6 55 io104nb6f6 52 io104pb6f6 53 io105nb6f6 48 io105pb6f6 49 io106nb6f6 46 io106pb6f6 47 bank 7 io107nb7f7 40 io107pb7f7 41 io108nb7f7 42 io108pb7f7 43 io109nb7f7 36 io109pb7f7 37 io110nb7f7 34 352-pin cqfp rtax250s/sl function pin number io110pb7f7 35 io111nb7f7 30 io111pb7f7 31 io113nb7f7 28 io113pb7f7 29 io114nb7f7 24 io114pb7f7 25 io115nb7f7 22 io115pb7f7 23 io116nb7f7 18 io116pb7f7 19 io117nb7f7 16 io117pb7f7 17 io118nb7f7 12 io118pb7f7 13 io119nb7f7 10 io119pb7f7 11 io121nb7f7 6 io121pb7f7 7 io123nb7f7 4 io123pb7f7 5 dedicated i/o gnd 1 gnd 9 gnd 15 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 352-pin cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas 3-12 v5.4 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 352-pin cqfp rtax250s/sl function pin number gnd 334 gnd 340 gnd 345 gnd 352 nc 91 nc 117 nc 124 nc 125 nc 126 nc 127 nc 130 nc 131 nc 138 nc 139 nc 140 nc 141 nc 148 nc 174 nc 268 nc 294 nc 301 nc 302 nc 303 nc 304 nc 307 nc 308 nc 315 nc 316 nc 317 nc 318 nc 327 nc 328 pra 312 prb 311 prc 135 prd 134 tck 349 352-pin cqfp rtax250s/sl function pin number tdi 348 tdo 347 tms 350 trst 351 v cca 3 v cca 14 v cca 32 v cca 56 v cca 74 v cca 87 v cca 102 v cca 114 v cca 150 v cca 162 v cca 175 v cca 191 v cca 209 v cca 233 v cca 251 v cca 263 v cca 279 v cca 291 v cca 329 v cca 339 v ccda 2 v ccda 44 v ccda 90 v ccda 116 v ccda 132 v ccda 149 v ccda 178 v ccda 221 v ccda 266 v ccda 293 v ccda 309 v ccda 346 v cci b0 321 352-pin cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-13 v cci b0 333 v cci b0 344 v cci b1 273 v cci b1 285 v cci b1 297 v cci b2 227 v cci b2 239 v cci b2 245 v cci b2 257 v cci b3 185 352-pin cqfp rtax250s/sl function pin number v cci b3 197 v cci b3 203 v cci b3 215 v cci b4 144 v cci b4 156 v cci b4 168 v cci b5 96 v cci b5 108 v cci b5 120 352-pin cqfp rtax250s/sl function pin number v cci b6 50 v cci b6 62 v cci b6 68 v cci b6 80 v cci b7 8 v cci b7 20 v cci b7 26 v cci b7 38 v pump 267 352-pin cqfp rtax250s/sl function pin number
rtax-s/sl radtolerant fpgas 3-14 v5.4 352-pin cqfp rtax1000s/sl function pin number bank 0 io02nb0f0 341 io02pb0f0 342 io03pb0f0 343 io04nb0f0 337 io04pb0f0 338 io08nb0f0 331 io08pb0f0 332 io09nb0f0 335 io09pb0f0 336 io24nb0f2 325 io24pb0f2 326 io25nb0f2 323 io25pb0f2 324 io30nb0f2/hclkan 319 io30pb0f2/hclkap 320 io31nb0f2/hclkbn 313 io31pb0f2/hclkbp 314 bank 1 io32nb1f3/hclkcn 305 io32pb1f3/hclkcp 306 io33nb1f3/hclkdn 299 io33pb1f3/hclkdp 300 io38nb1f3 295 io38pb1f3 296 io54nb1f5 287 io54pb1f5 288 io55nb1f5 289 io55pb1f5 290 io56nb1f5 281 io56pb1f5 282 io57nb1f5 283 io57pb1f5 284 io59nb1f5 277 io59pb1f5 278 io60nb1f5 275 io60pb1f5 276 io61nb1f5 271 io61pb1f5 272 io63nb1f5 269 io63pb1f5 270 bank 2 io64nb2f6 259 io64pb2f6 260 io67nb2f6 261 io67pb2f6 262 io68nb2f6 255 io68pb2f6 256 io69nb2f6 253 io69pb2f6 254 io74nb2f7 249 io74pb2f7 250 io75nb2f7 247 io75pb2f7 248 io76nb2f7 243 io76pb2f7 244 io77nb2f7 241 io77pb2f7 242 io78nb2f7 237 io78pb2f7 238 io79nb2f7 235 io79pb2f7 236 io82nb2f7 231 io82pb2f7 232 io83nb2f7 229 io83pb2f7 230 io94nb2f8 225 io94pb2f8 226 io95nb2f8 223 io95pb2f8 224 bank 3 io96nb3f9 217 io96pb3f9 218 io97nb3f9 219 352-pin cqfp rtax1000s/sl function pin number io97pb3f9 220 io99nb3f9 213 io99pb3f9 214 io108nb3f10 211 io108pb3f10 212 io109nb3f10 207 io109pb3f10 208 io111nb3f10 205 io111pb3f10 206 io112nb3f10 199 io112pb3f10 200 io113nb3f10 201 io113pb3f10 202 io115nb3f10 195 io115pb3f10 196 io116nb3f10 193 io116pb3f10 194 io117nb3f10 189 io117pb3f10 190 io124nb3f11 183 io124pb3f11 184 io125nb3f11 187 io125pb3f11 188 io127nb3f11 181 io127pb3f11 182 io128nb3f11 179 io128pb3f11 180 bank 4 io130nb4f12 172 io130pb4f12 173 io131nb4f12 170 io131pb4f12 171 io132nb4f12 166 io132pb4f12 167 io133nb4f12 164 io133pb4f12 165 io134nb4f12 160 352-pin cqfp rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-15 io134pb4f12 161 io136nb4f12 158 io136pb4f12 159 io137nb4f12 154 io137pb4f12 155 io138nb4f12 152 io138pb4f12 153 io153nb4f14 146 io153pb4f14 147 io159nb4f14/clken 142 io159pb4f14/clkep 143 io160nb4f14/clkfn 136 io160pb4f14/clkfp 137 bank 5 io161nb5f15/clkgn 128 io161pb5f15/clkgp 129 io162nb5f15/clkhn 122 io162pb5f15/clkhp 123 io167nb5f15 118 io167pb5f15 119 io183nb5f17 110 io183pb5f17 111 io184nb5f17 112 io184pb5f17 113 io185nb5f17 104 io185pb5f17 105 io186nb5f17 106 io186pb5f17 107 io187nb5f17 98 io187pb5f17 99 io188nb5f17 100 io188pb5f17 101 io190nb5f17 94 io190pb5f17 95 io192nb5f17 92 io192pb5f17 93 bank 6 352-pin cqfp rtax1000s/sl function pin number io193pb6f18 86 io194nb6f18 84 io194pb6f18 85 io196nb6f18 78 io196pb6f18 79 io197nb6f18 82 io197pb6f18 83 io198nb6f18 76 io198pb6f18 77 io203nb6f19 72 io203pb6f19 73 io204nb6f19 70 io204pb6f19 71 io205nb6f19 66 io205pb6f19 67 io206nb6f19 64 io206pb6f19 65 io207nb6f19 60 io207pb6f19 61 io208nb6f19 58 io208pb6f19 59 io211nb6f19 54 io211pb6f19 55 io212nb6f19 52 io212pb6f19 53 io223nb6f20 48 io223pb6f20 49 io224nb6f20 46 io224pb6f20 47 bank 7 io225nb7f21 40 io225pb7f21 41 io226nb7f21 42 io226pb7f21 43 io237nb7f22 34 io237pb7f22 35 io238nb7f22 36 352-pin cqfp rtax1000s/sl function pin number io238pb7f22 37 io240nb7f22 30 io240pb7f22 31 io241nb7f22 28 io241pb7f22 29 io242nb7f22 24 io242pb7f22 25 io244nb7f22 22 io244pb7f22 23 io245nb7f22 18 io245pb7f22 19 io246nb7f22 16 io246pb7f22 17 io249nb7f23 12 io249pb7f23 13 io250nb7f23 10 io250pb7f23 11 io256nb7f23 4 io256pb7f23 5 io257nb7f23 6 io257pb7f23 7 dedicated i/o gnd 1 gnd 9 gnd 15 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 352-pin cqfp rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-16 v5.4 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 352-pin cqfp rtax1000s/sl function pin number gnd 334 gnd 340 gnd 345 gnd 352 nc 91 nc 124 nc 125 nc 126 nc 127 nc 130 nc 131 nc 138 nc 139 nc 140 nc 141 nc 174 nc 268 nc 301 nc 302 nc 303 nc 304 nc 307 nc 308 nc 315 nc 316 nc 317 nc 318 pra 312 prb 311 prc 135 prd 134 tck 349 tdi 348 tdo 347 tms 350 trst 351 v cca 3 352-pin cqfp rtax1000s/sl function pin number v cca 14 v cca 32 v cca 56 v cca 74 v cca 87 v cca 102 v cca 114 v cca 150 v cca 162 v cca 175 v cca 191 v cca 209 v cca 233 v cca 251 v cca 263 v cca 279 v cca 291 v cca 329 v cca 339 v ccda 2 v ccda 44 v ccda 90 v ccda 116 v ccda 117 v ccda 132 v ccda 148 v ccda 149 v ccda 178 v ccda 221 v ccda 266 v ccda 293 v ccda 294 v ccda 309 v ccda 327 v ccda 328 v ccda 346 v cci b0 321 352-pin cqfp rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-17 v cci b0 333 v cci b0 344 v cci b1 273 v cci b1 285 v cci b1 297 v cci b2 227 v cci b2 239 v cci b2 245 v cci b2 257 v cci b3 185 352-pin cqfp rtax1000s/sl function pin number v cci b3 197 v cci b3 203 v cci b3 215 v cci b4 144 v cci b4 156 v cci b4 168 v cci b5 96 v cci b5 108 v cci b5 120 352-pin cqfp rtax1000s/sl function pin number v cci b6 50 v cci b6 62 v cci b6 68 v cci b6 80 v cci b7 8 v cci b7 20 v cci b7 26 v cci b7 38 v pump 267 352-pin cqfp rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-18 v5.4 352-pin cqfp rtax2000s/sl function pin number bank 0 io01nb0f0 341 io01pb0f0 342 io02pb0f0 343 io04nb0f0 337 io04pb0f0 338 io05nb0f0 335 io05pb0f0 336 io08nb0f0 331 io08pb0f0 332 io37nb0f3 325 io37pb0f3 326 io38nb0f3 323 io38pb0f3 324 io41nb0f3/hclkan 319 io41pb0f3/hclkap 320 io42nb0f3/hclkbn 313 io42pb0f3/hclkbp 314 bank 1 io43nb1f4/hclkcn 305 io43pb1f4/hclkcp 306 io44nb1f4/hclkdn 299 io44pb1f4/hclkdp 300 io48nb1f4 295 io48pb1f4 296 io65nb1f6 283 io65pb1f6 284 io66nb1f6 289 io66pb1f6 290 io68nb1f6 287 io68pb1f6 288 io69nb1f6 275 io69pb1f6 276 io70nb1f6 281 io70pb1f6 282 io71nb1f6 277 io71pb1f6 278 io73nb1f6 269 io73pb1f6 270 io74nb1f6 271 io74pb1f6 272 bank 2 io87nb2f8 261 io87pb2f8 262 io88nb2f8 255 io88pb2f8 256 io89nb2f8 259 io89pb2f8 260 io91nb2f8 253 io91pb2f8 254 io99nb2f9 249 io99pb2f9 250 io100nb2f9 247 io100pb2f9 248 io107nb2f10 243 io107pb2f10 244 io110nb2f10 241 io110pb2f10 242 io111nb2f10 237 io111pb2f10 238 io112nb2f10 235 io112pb2f10 236 io113nb2f10 231 io113pb2f10 232 io114nb2f10 229 io114pb2f10 230 io115nb2f10 225 io115pb2f10 226 io117nb2f10 223 io117pb2f10 224 bank 3 io129nb3f12 219 io129pb3f12 220 io132nb3f12 217 352-pin cqfp rtax2000s/sl function pin number io132pb3f12 218 io137nb3f12 213 io137pb3f12 214 io139nb3f13 211 io139pb3f13 212 io141nb3f13 205 io141pb3f13 206 io142nb3f13 207 io142pb3f13 208 io145nb3f13 199 io145pb3f13 200 io146nb3f13 201 io146pb3f13 202 io147nb3f13 193 io147pb3f13 194 io148nb3f13 195 io148pb3f13 196 io149nb3f13 189 io149pb3f13 190 io161nb3f15 183 io161pb3f15 184 io163nb3f15 187 io163pb3f15 188 io165nb3f15 181 io165pb3f15 182 io167nb3f15 179 io167pb3f15 180 bank 4 io181nb4f17 172 io181pb4f17 173 io182nb4f17 170 io182pb4f17 171 io183nb4f17 166 io183pb4f17 167 io184nb4f17 164 io184pb4f17 165 io185nb4f17 160 352-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-19 io185pb4f17 161 io190nb4f17 158 io190pb4f17 159 io191nb4f17 154 io191pb4f17 155 io192nb4f17 152 io192pb4f17 153 io207nb4f19 146 io207pb4f19 147 io212nb4f19/clken 142 io212pb4f19/clkep 143 io213nb4f19/clkfn 136 io213pb4f19/clkfp 137 bank 5 io214nb5f20/clkgn 128 io214pb5f20/clkgp 129 io215nb5f20/clkhn 122 io215pb5f20/clkhp 123 io217nb5f20 118 io217pb5f20 119 io236nb5f22 110 io236pb5f22 111 io237nb5f22 112 io237pb5f22 113 io238nb5f22 104 io238pb5f22 105 io239nb5f22 106 io239pb5f22 107 io240nb5f22 100 io240pb5f22 101 io242nb5f22 94 io242pb5f22 95 io243nb5f22 98 io243pb5f22 99 io244nb5f22 92 io244pb5f22 93 bank 6 352-pin cqfp rtax2000s/sl function pin number io257pb6f24 86 io258nb6f24 84 io258pb6f24 85 io261nb6f24 82 io261pb6f24 83 io262nb6f24 78 io262pb6f24 79 io265nb6f24 76 io265pb6f24 77 io279nb6f26 72 io279pb6f26 73 io280nb6f26 70 io280pb6f26 71 io281nb6f26 66 io281pb6f26 67 io282nb6f26 64 io282pb6f26 65 io284nb6f26 60 io284pb6f26 61 io285nb6f26 58 io285pb6f26 59 io286nb6f26 54 io286pb6f26 55 io287nb6f26 52 io287pb6f26 53 io294nb6f27 48 io294pb6f27 49 io296nb6f27 46 io296pb6f27 47 bank 7 io300nb7f28 42 io300pb7f28 43 io303nb7f28 40 io303pb7f28 41 io310nb7f29 34 io310pb7f29 35 io311nb7f29 36 352-pin cqfp rtax2000s/sl function pin number io311pb7f29 37 io312nb7f29 28 io312pb7f29 29 io315nb7f29 30 io315pb7f29 31 io316nb7f29 22 io316pb7f29 23 io317nb7f29 24 io317pb7f29 25 io318nb7f29 18 io318pb7f29 19 io320nb7f29 16 io320pb7f29 17 io334nb7f31 10 io334pb7f31 11 io335nb7f31 12 io335pb7f31 13 io338nb7f31 6 io338pb7f31 7 io341nb7f31 4 io341pb7f31 5 dedicated i/o gnd 1 gnd 9 gnd 15 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 352-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-20 v5.4 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 352-pin cqfp rtax2000s/sl function pin number gnd 334 gnd 340 gnd 345 gnd 352 nc 124 nc 125 nc 126 nc 127 nc 138 nc 139 nc 140 nc 141 nc 301 nc 302 nc 303 nc 304 nc 315 nc 316 nc 317 nc 318 pra 312 prb 311 prc 135 prd 134 tck 349 tdi 348 tdo 347 tms 350 trst 351 v cca 3 v cca 14 v cca 32 v cca 56 v cca 74 v cca 87 v cca 102 v cca 114 352-pin cqfp rtax2000s/sl function pin number v cca 150 v cca 162 v cca 175 v cca 191 v cca 209 v cca 233 v cca 251 v cca 263 v cca 279 v cca 291 v cca 329 v cca 339 v ccda 2 v ccda 44 v ccda 90 v ccda 91 v ccda 116 v ccda 117 v ccda 130 v ccda 131 v ccda 132 v ccda 148 v ccda 149 v ccda 174 v ccda 178 v ccda 221 v ccda 266 v ccda 268 v ccda 293 v ccda 294 v ccda 307 v ccda 308 v ccda 309 v ccda 327 v ccda 328 v ccda 346 v cci b0 321 352-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-21 v cci b0 333 v cci b0 344 v cci b1 273 v cci b1 285 v cci b1 297 v cci b2 227 v cci b2 239 v cci b2 245 v cci b2 257 v cci b3 185 352-pin cqfp rtax2000s/sl function pin number v cci b3 197 v cci b3 203 v cci b3 215 v cci b4 144 v cci b4 156 v cci b4 168 v cci b5 96 v cci b5 108 v cci b5 120 352-pin cqfp rtax2000s/sl function pin number v cci b6 50 v cci b6 62 v cci b6 68 v cci b6 80 v cci b7 8 v cci b7 20 v cci b7 26 v cci b7 38 v pump 267 352-pin cqfp rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-22 v5.4 352-pin cqfp rtax4000s/sl function pin number bank 0 io02nb0f0 341 io02pb0f0 342 io03pb0f0 343 io05nb0f0 337 io05pb0f0 338 io06nb0f0 335 io06pb0f0 336 io07nb0f0 331 io07pb0f0 332 io11nb0f0 329 io11pb0f0 330 io50nb0f4/hclkan 317 io50pb0f4/hclkap 318 io51nb0f4/hclkbn 313 io51pb0f4/hclkbp 314 bank 1 io52nb1f6/hclkcn 303 io52pb1f6/hclkcp 304 io53nb1f6/hclkdn 299 io53pb1f6/hclkdp 300 io94nb1f10 287 io94pb1f10 288 io97nb1f10 281 io97pb1f10 282 io98nb1f10 285 io98pb1f10 286 io99nb1f10 275 io99pb1f10 276 io100nb1f10 279 io100pb1f10 280 io102nb1f10 273 io102pb1f10 274 io103nb1f10 269 io103pb1f10 270 bank 2 io104nb2f12 259 io104pb2f12 260 io106nb2f12 253 io106pb2f12 254 io107nb2f12 257 io107pb2f12 258 io111nb2f12 251 io111pb2f12 252 io139nb2f16 241 io139pb2f16 242 io140nb2f16 245 io140pb2f16 246 io141nb2f16 235 io141pb2f16 236 io142nb2f16 239 io142pb2f16 240 io143nb2f16 229 io143pb2f16 230 io144nb2f16 233 io144pb2f16 234 io145nb2f16 223 io145pb2f16 224 io146nb2f16 227 io146pb2f16 228 bank 3 io175nb3f20 213 io175pb3f20 214 io176nb3f20 217 io176pb3f20 218 io177nb3f20 207 io177pb3f20 208 io178nb3f20 211 io178pb3f20 212 io179nb3f20 205 io179pb3f20 206 io181nb3f20 201 io181pb3f20 202 io182nb3f20 199 352-pin cqfp rtax4000s/sl function pin number io182pb3f20 200 io183nb3f20 195 io183pb3f20 196 io203nb3f23 189 io203pb3f23 190 io204nb3f23 183 io204pb3f23 184 io206nb3f23 187 io206pb3f23 188 io209nb3f23 181 io209pb3f23 182 bank 4 io210nb4f24 167 io210pb4f24 168 io211nb4f24 173 io213nb4f24 171 io213pb4f24 172 io214nb4f24 161 io214pb4f24 162 io215nb4f24 165 io215pb4f24 166 io216nb4f24 155 io216pb4f24 156 io217nb4f24 159 io217pb4f24 160 io219nb4f24 153 io219pb4f24 154 io260nb4f28/clken 141 io260pb4f28/clkep 142 io261nb4f28/clkfn 137 io261pb4f28/clkfp 138 bank 5 io262nb5f30/clkgn 127 io262pb5f30/clkgp 128 io263nb5f30/clkhn 123 io263pb5f30/clkhp 124 io304nb5f34 111 352-pin cqfp rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-23 io304pb5f34 112 io305nb5f34 109 io305pb5f34 110 io307nb5f34 103 io307pb5f34 104 io308nb5f34 105 io308pb5f34 106 io309nb5f34 97 io309pb5f34 98 io310nb5f34 99 io310pb5f34 100 io312nb5f34 93 io312pb5f34 94 io313nb5f34 92 bank 6 io314pb6f36 84 io316nb6f36 82 io316pb6f36 83 io317nb6f36 78 io317pb6f36 79 io319nb6f36 76 io319pb6f36 77 io349nb6f40 66 io349pb6f40 67 io350nb6f40 70 io350pb6f40 71 io351nb6f40 60 io351pb6f40 61 io352nb6f40 64 io352pb6f40 65 io353nb6f40 54 io353pb6f40 55 io354nb6f40 58 io354pb6f40 59 io355nb6f40 48 io355pb6f40 49 io356nb6f40 52 352-pin cqfp rtax4000s/sl function pin number io356pb6f40 53 bank 7 io385nb7f44 42 io385pb7f44 43 io386nb7f44 38 io386pb7f44 39 io387nb7f44 36 io387pb7f44 37 io388nb7f44 32 io388pb7f44 33 io389nb7f44 30 io389pb7f44 31 io391nb7f44 26 io391pb7f44 27 io392nb7f44 24 io392pb7f44 25 io393nb7f44 20 io393pb7f44 21 io413nb7f47 14 io413pb7f47 15 io414nb7f47 8 io414pb7f47 9 io416nb7f47 12 io416pb7f47 13 io419nb7f47 6 io419pb7f47 7 dedicated i/o gnd 1 gnd 5 gnd 11 gnd 17 gnd 19 gnd 23 gnd 29 gnd 35 gnd 41 gnd 45 352-pin cqfp rtax4000s/sl function pin number gnd 47 gnd 51 gnd 57 gnd 63 gnd 69 gnd 73 gnd 75 gnd 81 gnd 86 gnd 88 gnd 89 gnd 96 gnd 102 gnd 108 gnd 117 gnd 119 gnd 126 gnd 132 gnd 134 gnd 140 gnd 147 gnd 149 gnd 158 gnd 164 gnd 170 gnd 176 gnd 177 gnd 180 gnd 186 gnd 192 gnd 194 gnd 198 gnd 204 gnd 210 gnd 216 gnd 220 gnd 222 352-pin cqfp rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-24 v5.4 gnd 226 gnd 232 gnd 238 gnd 244 gnd 248 gnd 250 gnd 256 gnd 262 gnd 264 gnd 265 gnd 272 gnd 278 gnd 284 gnd 293 gnd 295 gnd 302 gnd 308 gnd 310 gnd 316 gnd 323 gnd 325 gnd 334 gnd 340 gnd 345 gnd 352 pra 312 prb 311 prc 136 prd 135 tck 349 tdi 348 tdo 347 tms 350 trst 351 v cca 3 v cca 4 v cca 18 352-pin cqfp rtax4000s/sl function pin number v cca 34 v cca 44 v cca 56 v cca 72 v cca 85 v cca 87 v cca 101 v cca 116 v cca 129 v cca 131 v cca 148 v cca 163 v cca 175 v cca 179 v cca 193 v cca 209 v cca 219 v cca 231 v cca 247 v cca 261 v cca 263 v cca 277 v cca 292 v cca 305 v cca 307 v cca 324 v cca 339 v ccda 2 v ccda 16 v ccda 46 v ccda 74 v ccda 90 v ccda 91 v ccda 113 v ccda 114 v ccda 115 v ccda 118 352-pin cqfp rtax4000s/sl function pin number v ccda 120 v ccda 121 v ccda 122 v ccda 130 v ccda 133 v ccda 143 v ccda 144 v ccda 145 v ccda 146 v ccda 150 v ccda 151 v ccda 152 v ccda 174 v ccda 178 v ccda 191 v ccda 221 v ccda 249 v ccda 266 v ccda 268 v ccda 289 v ccda 290 v ccda 291 v ccda 294 v ccda 296 v ccda 297 v ccda 298 v ccda 306 v ccda 309 v ccda 319 v ccda 320 v ccda 321 v ccda 322 v ccda 326 v ccda 327 v ccda 328 v ccda 346 v cci b0 315 352-pin cqfp rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-25 v cci b0 333 v cci b0 344 v cci b1 271 v cci b1 283 v cci b1 301 v cci b2 225 v cci b2 237 v cci b2 243 v cci b2 255 v cci b3 185 352-pin cqfp rtax4000s/sl function pin number v cci b3 197 v cci b3 203 v cci b3 215 v cci b4 139 v cci b4 157 v cci b4 169 v cci b5 95 v cci b5 107 v cci b5 125 352-pin cqfp rtax4000s/sl function pin number v cci b6 50 v cci b6 62 v cci b6 68 v cci b6 80 v cci b7 10 v cci b7 22 v cci b7 28 v cci b7 40 v pump 267 352-pin cqfp rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-26 v5.4 624-pin ccga/lga note: the 624-pin ccga pin assignments for rtax250s/sl, rtax10 00s/sl and rtax2000s/sl are co mpatible except for the following pins. where exceptions occur, the smaller density devices have those pins desi gnated as no connects (nc). customers are therefore recommended to layout their board targeting the larg er density device, in order to preserve interchangeability between the two devices. note: rtax4000s is not pin compatible with any of the smaller density devices. for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . figure 3-4 ? 624-pin ccga/lga (bottom view) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y a a ac ab ad ae table 3-2 ? compatibility table for the cga/lga 624 package rtax250s/sl rtax1000s/sl rtax2000s/sl rtax250s/sl na a12, ad11, ae17, b15, d13 a12, a14, aa20, ab13, ad11, ad4, ae12, b15, d13, f21, g10 rtax1000s/sl a12, ad11, ae17, b15, d13 na a14, aa20, ab13, ad4, ae12, f21, g10 rtax2000s/sl a12, a14, aa20, ab13, ad11, ad4, ae12, b15, d13, f21, g10 a14, aa20, ab13, ad4, ae12, f21, g10 na
rtax-s/sl radtolerant fpgas v5.4 3-27 624-pin ccga/lga rtax250s/sl pin function pin number bank 0 io00nb0f0 c9 io00pb0f0 c8 io01nb0f0 b5 io01pb0f0 b4 io02nb0f0 d10 io02pb0f0 d9 io03nb0f0 a5 io03pb0f0 a4 io04nb0f0 h8 io04pb0f0 h7 io05nb0f0 a7 io05pb0f0 a6 io06nb0f0 h10 io06pb0f0 h9 io07nb0f0 b11 io07pb0f0 b10 io08nb0f0 j8 io08pb0f0 j7 io09nb0f0 a9 io09pb0f0 b9 io12nb0f0/hclkan g13 io12pb0f0/hclkap g12 io13nb0f0/hclkbn c13 io13pb0f0/hclkbp c12 bank 1 io16nb1f1 d14 io16pb1f1 c14 io17nb1f1 a16 io17pb1f1 a15 io18nb1f1 h20 io18pb1f1 h19 io19nb1f1 b17 io19pb1f1 b16 io20nb1f1 d16 io20pb1f1 d15 io21nb1f1 a20 io21pb1f1 a19 io22nb1f1 d18 io22pb1f1 d17 io23nb1f1 a22 io23pb1f1 a21 io24nb1f1 g17 io24pb1f1 h17 io25nb1f1 c21 io25pb1f1 c20 io26nb1f1 c19 io26pb1f1 c18 io27nb1f1 d20 io27pb1f1 d19 io14nb1f1/hclkcn g15 io14pb1f1/hclkcp g14 io15nb1f1/hclkdn b14 io15pb1f1/hclkdp b13 bank 2 io28nb2f2 j22 io28pb2f2 h22 io29nb2f2 l18 io29pb2f2 k18 io30nb2f2 f23 io30pb2f2 e23 io31nb2f2 j21 io31pb2f2 j20 io32nb2f2 e25 io32pb2f2 d25 io33nb2f2 m19 io33pb2f2 m18 io34nb2f2 h23 io34pb2f2 g23 io35nb2f2 l22 io35pb2f2 k22 io36nb2f2 g25 io36pb2f2 f25 io37nb2f2 l24 624-pin ccga/lga rtax250s/sl pin function pin number io37pb2f2 k24 io38nb2f2 j24 io38pb2f2 h24 io39nb2f2 n22 io39pb2f2 m22 io40nb2f2 n24 io40pb2f2 m24 io41nb2f2 n19 io41pb2f2 n18 io42nb2f2 l25 io42pb2f2 k25 io43nb2f2 n23 io43pb2f2 m23 io44nb2f2 n25 io44pb2f2 m25 bank 3 io45nb3f3 r22 io45pb3f3 p22 io46nb3f3 r25 io46pb3f3 p25 io47nb3f3 r23 io47pb3f3 p23 io48nb3f3 y25 io48pb3f3 w25 io49nb3f3 u24 io49pb3f3 u23 io50nb3f3 t24 io50pb3f3 r24 io51nb3f3 y23 io51pb3f3 aa23 io52nb3f3 v23 io52pb3f3 v24 io53nb3f3 p20 io53pb3f3 p19 io54nb3f3 u25 io54pb3f3 t25 io55nb3f3 v22 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas 3-28 v5.4 io55pb3f3 u22 io56nb3f3 aa24 io56pb3f3 y24 io57nb3f3 v20 io57pb3f3 u20 io58nb3f3 ab25 io58pb3f3 aa25 io59nb3f3 y22 io59pb3f3 y21 io60nb3f3 w22 io60pb3f3 w23 io61nb3f3 t18 io61pb3f3 r18 bank 4 io62nb4f4 v19 io62pb4f4 w19 io63nb4f4 ae19 io63pb4f4 ae20 io64nb4f4 w18 io64pb4f4 v18 io65nb4f4 ac20 io65pb4f4 ac21 io66nb4f4 ad14 io66pb4f4 ac14 io67nb4f4 ad21 io67pb4f4 ad22 io68nb4f4 ad15 io68pb4f4 ad16 io69nb4f4 ad19 io69pb4f4 ad20 io70nb4f4 ab14 io70pb4f4 ab15 io71nb4f4 ad17 io71pb4f4 ad18 io72nb4f4 v15 io72pb4f4 v16 io73nb4f4 ae15 624-pin ccga/lga rtax250s/sl pin function pin number io73pb4f4 ae16 io74nb4f4/clken w14 io74pb4f4/clkep w15 io75nb4f4/clkfn ac13 io75pb4f4/clkfp ad13 bank 5 io78nb5f5 ae10 io78pb5f5 ae11 io79nb5f5 ad9 io79pb5f5 ad10 io80nb5f5 v9 io80pb5f5 v10 io81nb5f5 ad7 io81pb5f5 ad8 io82nb5f5 ab10 io82pb5f5 ab11 io83nb5f5 ae6 io83pb5f5 ae7 io84nb5f5 ab8 io84pb5f5 ac8 io85nb5f5 ae4 io85pb5f5 ae5 io86nb5f5 u13 io86pb5f5 v13 io87nb5f5 ac5 io87pb5f5 ac6 io88nb5f5 y7 io88pb5f5 w7 io89nb5f5 ab7 io89pb5f5 ac7 io76nb5f5/clkgn w13 io76pb5f5/clkgp y13 io77nb5f5/clkhn ac12 io77pb5f5/clkhp ad12 bank 6 io90nb6f6 y3 io90pb6f6 aa3 624-pin ccga/lga rtax250s/sl pin function pin number io91nb6f6 u4 io91pb6f6 v4 io92nb6f6 aa1 io92pb6f6 ab1 io93nb6f6 w2 io93pb6f6 y2 io94nb6f6 v3 io94pb6f6 w3 io95nb6f6 r4 io95pb6f6 t4 io96nb6f6 w1 io96pb6f6 y1 io97nb6f6 y5 io97pb6f6 w5 io98nb6f6 t2 io98pb6f6 u2 io99nb6f6 n3 io99pb6f6 p3 io100nb6f6 t1 io100pb6f6 u1 io101nb6f6 n4 io101pb6f6 p4 io102nb6f6 p2 io102pb6f6 r2 io103nb6f6 r8 io103pb6f6 t8 io104nb6f6 p1 io104pb6f6 r1 io105nb6f6 m2 io105pb6f6 n2 io106nb6f6 m1 io106pb6f6 n1 bank 7 io107nb7f7 h4 io107pb7f7 j4 io108nb7f7 k1 io108pb7f7 l1 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas v5.4 3-29 io109nb7f7 l3 io109pb7f7 m3 io10nb0f0 d12 io10pb0f0 d11 io110nb7f7 j2 io110pb7f7 j1 io111nb7f7 n10 io111pb7f7 n9 io112nb7f7 k2 io112pb7f7 l2 io113nb7f7 k8 io113pb7f7 l8 io114nb7f7 f1 io114pb7f7 g1 io115nb7f7 j6 io115pb7f7 j5 io116nb7f7 h3 io116pb7f7 h2 io117nb7f7 k4 io117pb7f7 l4 io118nb7f7 e2 io118pb7f7 f2 io119nb7f7 m9 io119pb7f7 m8 io11nb0f0 a11 io11pb0f0 a10 io120nb7f7 d1 io120pb7f7 e1 io121nb7f7 f3 io121pb7f7 e3 io122nb7f7 g4 io122pb7f7 g3 io123nb7f7 h5 io123pb7f7 h6 dedicated io gnd k5 gnd t5 624-pin ccga/lga rtax250s/sl pin function pin number gnd v5 gnd aa10 gnd aa16 gnd aa18 gnd t21 gnd k21 gnd h21 gnd e16 gnd e10 gnd e8 gnd a18 gnd a2 gnd a24 gnd a25 gnd a8 gnd aa21 gnd aa5 gnd ab22 gnd ab4 gnd ac10 gnd ac16 gnd ac23 gnd ac3 gnd ad1 gnd ad2 gnd ad24 gnd ad25 gnd ae1 gnd ae18 gnd ae2 gnd ae24 gnd ae25 gnd ae8 gnd b1 gnd b2 gnd b24 gnd b25 624-pin ccga/lga rtax250s/sl pin function pin number gnd c10 gnd c16 gnd c23 gnd c3 gnd d22 gnd d4 gnd e21 gnd e5 gnd h1 gnd h25 gnd k23 gnd k3 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas 3-30 v5.4 gnd t23 gnd t3 gnd v1 gnd v25 nc a12 nc a14 nc a17 nc aa11 nc aa12 nc aa14 nc aa17 nc aa19 nc aa2 nc aa20 nc aa6 nc aa8 nc aa9 nc ab13 nc ab16 nc ab17 nc ab18 nc ab19 nc ab2 nc ab24 nc ab6 nc ab9 nc ac15 nc ac17 nc ac18 nc ac19 nc ac9 nc ad11 nc ad4 nc ad5 nc ad6 nc ae12 nc ae14 624-pin ccga/lga rtax250s/sl pin function pin number nc ae17 nc ae21 nc ae22 nc ae9 nc b12 nc b15 nc b18 nc b19 nc b20 nc b21 nc b22 nc b6 nc b7 nc b8 nc c11 nc c17 nc c7 nc d13 nc d2 nc d24 nc d7 nc d8 nc e11 nc e12 nc e14 nc e15 nc e17 nc e18 nc e24 nc e7 nc e9 nc f10 nc f11 nc f12 nc f14 nc f15 nc f16 624-pin ccga/lga rtax250s/sl pin function pin number nc f17 nc f18 nc f19 nc f20 nc f21 nc f24 nc f7 nc f8 nc f9 nc g10 nc g11 nc g16 nc g18 nc g19 nc g2 nc g20 nc g21 nc g22 nc g24 nc g6 nc g7 nc g8 nc g9 nc h11 nc h12 nc h13 nc h14 nc h15 nc h16 nc h18 nc j12 nc j13 nc j14 nc j18 nc j19 nc j23 nc j25 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas v5.4 3-31 nc j3 nc k13 nc k19 nc k20 nc k6 nc k7 nc l19 nc l20 nc l21 nc l23 nc l5 nc l6 nc l7 nc m17 nc m20 nc m21 nc m4 nc m5 nc m6 nc m7 nc n16 nc n17 nc n20 nc n6 nc n7 nc n8 nc p17 nc p18 nc p21 nc p24 nc p5 nc p6 nc p7 nc p8 nc p9 nc r19 nc r20 624-pin ccga/lga rtax250s/sl pin function pin number nc r21 nc r3 nc r5 nc r6 nc r7 nc t13 nc t19 nc t20 nc t22 nc t6 nc t7 nc u12 nc u14 nc u18 nc u19 nc u21 nc u3 nc u5 nc u6 nc u7 nc u8 nc v11 nc v12 nc v14 nc v17 nc v2 nc v21 nc v6 nc v7 nc v8 nc w10 nc w11 nc w12 nc w16 nc w17 nc w20 nc w24 624-pin ccga/lga rtax250s/sl pin function pin number nc w4 nc w6 nc w8 nc w9 nc y10 nc y11 nc y12 nc y14 nc y15 nc y16 nc y17 nc y18 nc y19 nc y20 nc y6 nc y8 nc y9 pra f13 prb a13 prc ab12 prd ae13 tck f5 tdi c5 tdo f6 tms d6 trst e6 v cca f4 v cca y4 v cca ab20 v cca f22 v cca j17 v cca j9 v cca k10 v cca k11 v cca k15 v cca k16 v cca l10 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas 3-32 v5.4 v cca l16 v cca r10 v cca r16 v cca t10 v cca t11 v cca t15 v cca t16 v cca u17 v cca u9 v ccda g5 v ccda n5 v ccda aa7 v ccda ac11 v ccda aa13 v ccda aa15 v ccda w21 v ccda n21 v ccda e19 v ccda c15 v ccda e13 v ccda c6 v cci b0 a3 v cci b0 b3 v cci b0 c4 v cci b0 d5 v cci b0 j10 v cci b0 j11 v cci b0 k12 v cci b1 a23 v cci b1 b23 v cci b1 c22 v cci b1 d21 v cci b1 j15 v cci b1 j16 v cci b1 k14 v cci b2 c24 v cci b2 c25 624-pin ccga/lga rtax250s/sl pin function pin number v cci b2 d23 v cci b2 e22 v cci b2 k17 v cci b2 l17 v cci b2 m16 v cci b3 aa22 v cci b3 ab23 v cci b3 ac24 v cci b3 ac25 v cci b3 p16 v cci b3 r17 v cci b3 t17 v cci b4 ab21 v cci b4 ac22 v cci b4 ad23 v cci b4 ae23 v cci b4 t14 v cci b4 u15 v cci b4 u16 v cci b5 ab5 v cci b5 ac4 v cci b5 ad3 v cci b5 ae3 v cci b5 t12 v cci b5 u10 v cci b5 u11 v cci b6 aa4 v cci b6 ab3 v cci b6 ac1 v cci b6 ac2 v cci b6 p10 v cci b6 r9 v cci b6 t9 v cci b7 c1 v cci b7 c2 v cci b7 d3 v cci b7 e4 624-pin ccga/lga rtax250s/sl pin function pin number v cci b7 k9 v cci b7 l9 v cci b7 m10 v pump e20 624-pin ccga/lga rtax250s/sl pin function pin number
rtax-s/sl radtolerant fpgas v5.4 3-33 624-pin ccga/lga rtax1000s/sl function pin number bank 0 io00nb0f0 f8 io00pb0f0 f7 io02nb0f0 g7 io02pb0f0 g6 io04nb0f0 e9 io04pb0f0 d8 io06nb0f0 g9 io06pb0f0 g8 io07pb0f0 b6 io08nb0f0 f10 io08pb0f0 f9 io09pb0f0 c7 io10nb0f0 h8 io10pb0f0 h7 io11nb0f0 d10 io11pb0f0 d9 io12nb0f1 b5 io12pb0f1 b4 io13nb0f1 a7 io13pb0f1 a6 io14nb0f1 c9 io14pb0f1 c8 io15pb0f1 b7 io16nb0f1 a5 io16pb0f1 a4 io17nb0f1 a9 io17pb0f1 b9 io18nb0f1 d12 io18pb0f1 d11 io20nb0f1 b11 io20pb0f1 b10 io21nb0f1 a11 io21pb0f1 a10 io22nb0f2 h10 io22pb0f2 h9 io23nb0f2 e11 io23pb0f2 f11 io24nb0f2 d7 io24pb0f2 e7 io25pb0f2 b12 io26nb0f2 h11 io26pb0f2 g11 io27nb0f2 c11 io27pb0f2 b8 io28nb0f2 j13 io28pb0f2 k13 io29nb0f2 j8 io29pb0f2 j7 io30nb0f2/hclkan g13 io30pb0f2/hclkap g12 io31nb0f2/hclkbn c13 io31pb0f2/hclkbp c12 bank 1 io32nb1f3/hclkcn g15 io32pb1f3/hclkcp g14 io33nb1f3/hclkdn b14 io33pb1f3/hclkdp b13 io34nb1f3 g16 io34pb1f3 h16 io35nb1f3 c17 io35pb1f3 b18 io36nb1f3 h18 io36pb1f3 h15 io37nb1f3 h13 io38nb1f3 e15 io38pb1f3 f15 io39nb1f3 d14 io39pb1f3 c14 io40nb1f3 d16 io40pb1f3 d15 io41nb1f4 f16 624-pin ccga/lga rtax1000s/sl function pin number io42nb1f4 g21 io42pb1f4 g20 io43nb1f4 a16 io43pb1f4 a15 io44nb1f4 a20 io44pb1f4 a19 io45nb1f4 b17 io45pb1f4 b16 io46nb1f4 g17 io46pb1f4 h17 io47nb1f4 a17 io48nb1f4 c19 io48pb1f4 c18 io49nb1f4 b20 io49pb1f4 b19 io50nb1f4 h20 io50pb1f4 h19 io51nb1f4 a22 io51pb1f4 a21 io52nb1f4 c21 io52pb1f4 c20 io53nb1f4 b22 io53pb1f4 b21 io54nb1f5 j18 io54pb1f5 j19 io55nb1f5 d18 io55pb1f5 d17 io56nb1f5 f20 io56pb1f5 f19 io58nb1f5 e17 io58pb1f5 f17 io60nb1f5 d20 io60pb1f5 d19 io62nb1f5 e18 io62pb1f5 f18 io63nb1f5 g19 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-34 v5.4 io63pb1f5 g18 bank 2 io64nb2f6 m17 io64pb2f6 g22 io65nb2f6 j21 io65pb2f6 j20 io66nb2f6 l23 io66pb2f6 k20 io67nb2f6 f23 io67pb2f6 e23 io68nb2f6 l18 io68pb2f6 k18 io70nb2f6 e24 io70pb2f6 d24 io71nb2f6 h23 io71pb2f6 g23 io72nb2f6 l19 io72pb2f6 k19 io74nb2f7 j22 io74pb2f7 h22 io75nb2f7 n23 io75pb2f7 m23 io76nb2f7 n17 io76pb2f7 n16 io77nb2f7 l22 io77pb2f7 k22 io78nb2f7 m19 io78pb2f7 m18 io79nb2f7 n19 io79pb2f7 n18 io80nb2f7 l21 io80pb2f7 l20 io82nb2f7 p18 io82pb2f7 p17 io83nb2f7 n22 io83pb2f7 m22 624-pin ccga/lga rtax1000s/sl function pin number io84nb2f7 m20 io84pb2f7 m21 io86nb2f8 e25 io86pb2f8 d25 io87nb2f8 l24 io87pb2f8 k24 io88nb2f8 g24 io88pb2f8 f24 io89nb2f8 j25 io90nb2f8 g25 io90pb2f8 f25 io91nb2f8 l25 io91pb2f8 k25 io92nb2f8 j24 io92pb2f8 h24 io93pb2f8 j23 io94nb2f8 n24 io94pb2f8 m24 io95nb2f8 n25 io95pb2f8 m25 bank 3 io96nb3f9 t18 io96pb3f9 r18 io97nb3f9 n20 io97pb3f9 p24 io98nb3f9 p20 io98pb3f9 p19 io99nb3f9 p21 io100nb3f9 t22 io100pb3f9 w24 io101nb3f9 r22 io101pb3f9 p22 io102nb3f9 u19 io102pb3f9 t19 io104nb3f9 v20 io104pb3f9 u20 624-pin ccga/lga rtax1000s/sl function pin number io105nb3f9 r23 io105pb3f9 p23 io106nb3f9 r19 io106pb3f9 r20 io107nb3f10 ab24 io108nb3f10 r25 io108pb3f10 p25 io109nb3f10 u25 io109pb3f10 t25 io110nb3f10 u24 io110pb3f10 u23 io112nb3f10 t24 io112pb3f10 r24 io113nb3f10 y25 io113pb3f10 w25 io114nb3f10 v23 io114pb3f10 v24 io116nb3f10 aa24 io116pb3f10 y24 io117nb3f10 ab25 io117pb3f10 aa25 io118nb3f11 t20 io118pb3f11 r21 io120nb3f11 w22 io120pb3f11 w23 io122nb3f11 v22 io122pb3f11 u22 io124nb3f11 y23 io124pb3f11 aa23 io126nb3f11 v21 io126pb3f11 u21 io128nb3f11 y22 io128pb3f11 y21 bank 4 io129nb4f12 w20 io129pb4f12 y20 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-35 io131nb4f12 v19 io131pb4f12 w19 io133nb4f12 y18 io133pb4f12 y19 io135nb4f12 w18 io135pb4f12 v18 io137nb4f12 y17 io137pb4f12 aa17 io138nb4f12 ab19 io138pb4f12 ab18 io139nb4f13 aa19 io139pb4f13 u18 io140nb4f13 ac20 io140pb4f13 ac21 io141nb4f13 ad17 io141pb4f13 ad18 io142nb4f13 ad21 io142pb4f13 ad22 io143nb4f13 ab17 io143pb4f13 ac17 io144pb4f13 ae22 io145nb4f13 ae15 io145pb4f13 ae16 io146nb4f13 ad19 io146pb4f13 ad20 io147nb4f13 ad15 io147pb4f13 ad16 io148pb4f13 ae21 io149nb4f13 ad14 io149pb4f13 ac14 io150nb4f13 ae19 io150pb4f13 ae20 io151nb4f13 v17 io151pb4f13 w17 io152nb4f14 ab16 io152pb4f14 w16 624-pin ccga/lga rtax1000s/sl function pin number io153nb4f14 y15 io153pb4f14 y16 io155nb4f14 v15 io155pb4f14 v16 io156nb4f14 ab14 io156pb4f14 ab15 io157nb4f14 ae14 io157pb4f14 ac18 io158nb4f14 ac15 io158pb4f14 ac19 io159nb4f14/clken w14 io159pb4f14/clkep w15 io160nb4f14/clkfn ac13 io160pb4f14/clkfp ad13 bank 5 io161nb5f15/clkgn w13 io161pb5f15/clkgp y13 io162nb5f15/clkhn ac12 io162pb5f15/clkhp ad12 io163nb5f15 v9 io163pb5f15 v10 io164nb5f15 v11 io164pb5f15 t13 io165nb5f15 u13 io165pb5f15 v13 io167nb5f15 w11 io167pb5f15 w12 io168nb5f15 ab6 io168pb5f15 aa6 io169nb5f15 v8 io169pb5f15 v7 io171nb5f16 w8 io171pb5f16 w9 io172nb5f16 ab8 io172pb5f16 ac8 io173nb5f16 aa11 624-pin ccga/lga rtax1000s/sl function pin number io173pb5f16 y11 io174nb5f16 ab10 io174pb5f16 ab11 io175nb5f16 ac9 io175pb5f16 ae9 io177nb5f16 aa8 io177pb5f16 y8 io178nb5f16 y6 io178pb5f16 w6 io179nb5f16 y10 io179pb5f16 w10 io180nb5f16 y7 io180pb5f16 w7 io181nb5f17 ad9 io181pb5f17 ad10 io182nb5f17 ae10 io182pb5f17 ae11 io183nb5f17 ad7 io183pb5f17 ad8 io184nb5f17 ab9 io185nb5f17 ae6 io185pb5f17 ae7 io186nb5f17 ae4 io186pb5f17 ae5 io187nb5f17 aa9 io187pb5f17 y9 io188nb5f17 u8 io189nb5f17 ad5 io189pb5f17 ad6 io191nb5f17 ac5 io191pb5f17 ac6 io192nb5f17 ab7 io192pb5f17 ac7 bank 6 io193nb6f18 u6 io193pb6f18 u5 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-36 v5.4 io194nb6f18 y3 io194pb6f18 aa3 io195nb6f18 v6 io195pb6f18 w4 io197nb6f18 r5 io197pb6f18 u3 io198nb6f18 p6 io199nb6f18 y5 io199pb6f18 w5 io200nb6f18 v3 io200pb6f18 w3 io201nb6f18 t7 io201pb6f18 u7 io202nb6f18 v2 io203nb6f19 w2 io203pb6f19 y2 io204nb6f19 aa1 io204pb6f19 ab1 io205nb6f19 r6 io205pb6f19 t6 io206nb6f19 w1 io206pb6f19 y1 io207nb6f19 t2 io207pb6f19 u2 io208nb6f19 t1 io208pb6f19 u1 io209nb6f19 aa2 io209pb6f19 ab2 io210nb6f19 p5 io211nb6f19 m1 io211pb6f19 n1 io212nb6f19 p1 io212pb6f19 r1 io213nb6f19 r8 io213pb6f19 t8 io215nb6f20 u4 624-pin ccga/lga rtax1000s/sl function pin number io215pb6f20 v4 io216nb6f20 p8 io216pb6f20 r3 io217nb6f20 p7 io217pb6f20 r7 io219nb6f20 r4 io219pb6f20 t4 io220nb6f20 p2 io220pb6f20 r2 io221nb6f20 n4 io221pb6f20 p4 io223nb6f20 m2 io223pb6f20 n2 io224nb6f20 n3 io224pb6f20 p3 bank 7 io225nb7f21 j2 io225pb7f21 j1 io226pb7f21 g2 io227nb7f21 h3 io227pb7f21 h2 io229nb7f21 k2 io229pb7f21 l2 io230nb7f21 k1 io230pb7f21 l1 io231nb7f21 e2 io231pb7f21 f2 io232nb7f21 f1 io232pb7f21 g1 io233nb7f21 l3 io233pb7f21 m3 io234nb7f21 d1 io234pb7f21 e1 io235nb7f21 k4 io235pb7f21 l4 io236nb7f22 m6 624-pin ccga/lga rtax1000s/sl function pin number io237nb7f22 n8 io237pb7f22 n7 io238nb7f22 m5 io239nb7f22 l6 io239pb7f22 l5 io240nb7f22 m4 io241nb7f22 l7 io241pb7f22 m7 io242nb7f22 j3 io243nb7f22 m9 io243pb7f22 m8 io244nb7f22 p9 io244pb7f22 n6 io245nb7f22 k8 io245pb7f22 l8 io246nb7f22 f3 io246pb7f22 e3 io247nb7f23 k7 io247pb7f23 k6 io248nb7f23 d2 io249nb7f23 g4 io249pb7f23 g3 io251nb7f23 n10 io251pb7f23 n9 io253nb7f23 h4 io253pb7f23 j4 io255nb7f23 j6 io255pb7f23 j5 io257nb7f23 h5 io257pb7f23 h6 dedicated i/o gnd k5 gnd a18 gnd a2 gnd a24 gnd a25 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-37 gnd a8 gnd aa10 gnd aa16 gnd aa18 gnd aa21 gnd aa5 gnd ab22 gnd ab4 gnd ac10 gnd ac16 gnd ac23 gnd ac3 gnd ad1 gnd ad2 gnd ad24 gnd ad25 gnd ae1 gnd ae18 gnd ae2 gnd ae24 gnd ae25 gnd ae8 gnd b1 gnd b2 gnd b24 gnd b25 gnd c10 gnd c16 gnd c23 gnd c3 gnd d22 gnd d4 gnd e10 gnd e16 gnd e21 gnd e5 624-pin ccga/lga rtax1000s/sl function pin number gnd e8 gnd h1 gnd h21 gnd h25 gnd k21 gnd k23 gnd k3 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd t21 gnd t23 gnd t3 gnd t5 624-pin ccga/lga rtax1000s/sl function pin number gnd v1 gnd v25 gnd v5 nc a14 nc aa12 nc aa14 nc aa20 nc ab13 nc ad4 nc ae12 nc e12 nc e14 nc f12 nc f14 nc f21 nc g10 nc h12 nc h14 nc j12 nc j14 nc u12 nc u14 nc v12 nc v14 nc y12 nc y14 pra f13 prb a13 prc ab12 prd ae13 tck f5 tdi c5 tdo f6 tms d6 trst e6 v cca ab20 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-38 v5.4 v cca f22 v cca f4 v cca j17 v cca j9 v cca k10 v cca k11 v cca k15 v cca k16 v cca l10 v cca l16 v cca r10 v cca r16 v cca t10 v cca t11 v cca t15 v cca t16 v cca u17 v cca u9 v cca y4 v ccda a12 v ccda aa13 v ccda aa15 v ccda aa7 v ccda ac11 v ccda ad11 v ccda ae17 v ccda b15 v ccda c15 v ccda c6 v ccda d13 v ccda e13 v ccda e19 v ccda g5 v ccda n21 v ccda n5 v ccda w21 624-pin ccga/lga rtax1000s/sl function pin number v cci b0 a3 v cci b0 b3 v cci b0 c4 v cci b0 d5 v cci b0 j10 v cci b0 j11 v cci b0 k12 v cci b1 a23 v cci b1 b23 v cci b1 c22 v cci b1 d21 v cci b1 j15 v cci b1 j16 v cci b1 k14 v cci b2 c24 v cci b2 c25 v cci b2 d23 v cci b2 e22 v cci b2 k17 v cci b2 l17 v cci b2 m16 v cci b3 aa22 v cci b3 ab23 v cci b3 ac24 v cci b3 ac25 v cci b3 p16 v cci b3 r17 v cci b3 t17 v cci b4 ab21 v cci b4 ac22 v cci b4 ad23 v cci b4 ae23 v cci b4 t14 v cci b4 u15 v cci b4 u16 v cci b5 ab5 624-pin ccga/lga rtax1000s/sl function pin number v cci b5 ac4 v cci b5 ad3 v cci b5 ae3 v cci b5 t12 v cci b5 u10 v cci b5 u11 v cci b6 aa4 v cci b6 ab3 v cci b6 ac1 v cci b6 ac2 v cci b6 p10 v cci b6 r9 v cci b6 t9 v cci b7 c1 v cci b7 c2 v cci b7 d3 v cci b7 e4 v cci b7 k9 v cci b7 l9 v cci b7 m10 v pump e20 624-pin ccga/lga rtax1000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-39 624-pin ccga/lga rtax2000s/sl function pin number bank 0 io00nb0f0 d7 io00pb0f0 e7 io01nb0f0 g7 io01pb0f0 g6 io02nb0f0 b5 io02pb0f0 b4 io04pb0f0 c7 io05nb0f0 f8 io05pb0f0 f7 io06nb0f0 h8 io06pb0f0 h7 io11nb0f0 j8 io11pb0f0 j7 io12pb0f1 b6 io13nb0f1 e9 io13pb0f1 d8 io15nb0f1 c9 io15pb0f1 c8 io16nb0f1 a5 io16pb0f1 a4 io17nb0f1 d10 io17pb0f1 d9 io18nb0f1 a7 io18pb0f1 a6 io19nb0f1 g9 io19pb0f1 g8 io20pb0f1 b7 io23nb0f2 f10 io23pb0f2 f9 io26nb0f2 c11 io26pb0f2 b8 io27nb0f2 h10 io27pb0f2 h9 io28nb0f2 a9 io28pb0f2 b9 io30nb0f2 b11 io30pb0f2 b10 io31nb0f2 e11 io31pb0f2 f11 io33nb0f2 d12 io33pb0f2 d11 io34nb0f3 a11 io34pb0f3 a10 io37nb0f3 j13 io37pb0f3 k13 io38nb0f3 h11 io38pb0f3 g11 io40pb0f3 b12 io41nb0f3/hclkan g13 io41pb0f3/hclkap g12 io42nb0f3/hclkbn c13 io42pb0f3/hclkbp c12 bank 1 io43nb1f4/hclkcn g15 io43pb1f4/hclkcp g14 io44nb1f4/hclkdn b14 io44pb1f4/hclkdp b13 io45nb1f4 h13 io47nb1f4 d14 io47pb1f4 c14 io48nb1f4 a16 io48pb1f4 a15 io49pb1f4 h15 io51nb1f4 e15 io51pb1f4 f15 io52nb1f4 a17 io55nb1f5 g16 io55pb1f5 h16 io56nb1f5 a20 io56pb1f5 a19 io57nb1f5 d16 624-pin ccga/lga rtax2000s/sl function pin number io57pb1f5 d15 io58nb1f5 a22 io58pb1f5 a21 io59nb1f5 f16 io61nb1f5 g17 io61pb1f5 h17 io62nb1f5 b17 io62pb1f5 b16 io63nb1f5 h18 io65nb1f6 c17 io66pb1f6 b18 io67nb1f6 j18 io67pb1f6 j19 io68nb1f6 b20 io68pb1f6 b19 io69nb1f6 e17 io69pb1f6 f17 io70nb1f6 b22 io70pb1f6 b21 io71pb1f6 g18 io73nb1f6 g19 io74nb1f6 c19 io74pb1f6 c18 io75nb1f6 d18 io75pb1f6 d17 io76nb1f7 c21 io76pb1f7 c20 io79nb1f7 h20 io79pb1f7 h19 io80nb1f7 e18 io80pb1f7 f18 io81nb1f7 g21 io81pb1f7 g20 io82nb1f7 f20 io82pb1f7 f19 io85nb1f7 d20 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-40 v5.4 io85pb1f7 d19 bank 2 io86nb2f8 f23 io86pb2f8 e23 io87nb2f8 h23 io87pb2f8 g23 io88nb2f8 e24 io88pb2f8 d24 io89nb2f8 m17 io89pb2f8 g22 io91nb2f8 j22 io91pb2f8 h22 io92nb2f8 l18 io92pb2f8 k18 io96nb2f9 g24 io96pb2f9 f24 io97nb2f9 j21 io97pb2f9 j20 io98pb2f9 j23 io99nb2f9 l19 io99pb2f9 k19 io100nb2f9 e25 io100pb2f9 d25 io103pb2f9 k20 io105nb2f9 m19 io105pb2f9 m18 io106nb2f9 j24 io106pb2f9 h24 io107nb2f10 l23 io107pb2f10 n16 io109nb2f10 l22 io109pb2f10 k22 io110nb2f10 g25 io110pb2f10 f25 io111nb2f10 l21 io111pb2f10 l20 624-pin ccga/lga rtax2000s/sl function pin number io112nb2f10 l24 io112pb2f10 k24 io113nb2f10 n17 io115nb2f10 m20 io115pb2f10 m21 io117nb2f10 n19 io117pb2f10 n18 io118nb2f11 j25 io121nb2f11 n24 io121pb2f11 m24 io122nb2f11 l25 io122pb2f11 k25 io123nb2f11 n22 io123pb2f11 m22 io124nb2f11 n23 io124pb2f11 m23 io127nb2f11 p18 io127pb2f11 p17 io128nb2f11 n25 io128pb2f11 m25 bank 3 io129nb3f12 n20 io130pb3f12 p24 io131nb3f12 p21 io133nb3f12 p20 io133pb3f12 p19 io138nb3f12 r23 io138pb3f12 p23 io139nb3f13 r22 io139pb3f13 p22 io141nb3f13 r19 io142nb3f13 r25 io142pb3f13 p25 io143pb3f13 r21 io145nb3f13 t18 io145pb3f13 r18 624-pin ccga/lga rtax2000s/sl function pin number io146nb3f13 t24 io146pb3f13 r24 io147nb3f13 t20 io147pb3f13 r20 io148nb3f13 u25 io148pb3f13 t25 io149nb3f13 t22 io153nb3f14 u19 io153pb3f14 t19 io154nb3f14 y25 io154pb3f14 w25 io157nb3f14 v20 io157pb3f14 u20 io158nb3f14 ab25 io158pb3f14 aa25 io160pb3f14 w24 io161nb3f15 u24 io161pb3f15 u23 io162nb3f15 aa24 io162pb3f15 y24 io163nb3f15 v22 io163pb3f15 u22 io164nb3f15 v23 io164pb3f15 v24 io166nb3f15 ab24 io167nb3f15 v21 io167pb3f15 u21 io168nb3f15 y23 io168pb3f15 aa23 io169nb3f15 w22 io169pb3f15 w23 io170nb3f15 y22 io170pb3f15 y21 bank 4 io171nb4f16 ac20 io171pb4f16 ac21 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-41 io172nb4f16 w20 io172pb4f16 y20 io173nb4f16 ad21 io173pb4f16 ad22 io174nb4f16 aa19 io176nb4f16 y18 io176pb4f16 y19 io177nb4f16 ab19 io177pb4f16 ab18 io182nb4f17 v19 io182pb4f17 w19 io183pb4f17 ac19 io184nb4f17 ab17 io184pb4f17 ac17 io185nb4f17 ad19 io185pb4f17 ad20 io187pb4f17 ac18 io188nb4f17 y17 io188pb4f17 aa17 io189pb4f17 ae22 io191nb4f17 w18 io191pb4f17 v18 io192pb4f17 u18 io195pb4f18 ae21 io196nb4f18 ab16 io197nb4f18 ad17 io197pb4f18 ad18 io198nb4f18 v17 io198pb4f18 w17 io199nb4f18 ae19 io199pb4f18 ae20 io200nb4f18 ac15 io201nb4f18 ad15 io201pb4f18 ad16 io202nb4f18 y15 io202pb4f18 y16 624-pin ccga/lga rtax2000s/sl function pin number io206nb4f19 ab14 io206pb4f19 ab15 io207nb4f19 ae15 io207pb4f19 ae16 io208pb4f19 w16 io209nb4f19 ae14 io210nb4f19 v15 io210pb4f19 v16 io211nb4f19 ad14 io211pb4f19 ac14 io212nb4f19/clken w14 io212pb4f19/clkep w15 io213nb4f19/clkfn ac13 io213pb4f19/clkfp ad13 bank 5 io214nb5f20/clkgn w13 io214pb5f20/clkgp y13 io215nb5f20/clkhn ac12 io215pb5f20/clkhp ad12 io216nb5f20 u13 io216pb5f20 v13 io217nb5f20 ae10 io217pb5f20 ae11 io218nb5f20 w11 io218pb5f20 w12 io222nb5f20 aa11 io222pb5f20 y11 io223pb5f21 ae9 io225nb5f21 ae6 io225pb5f21 ae7 io226nb5f21 y10 io226pb5f21 w10 io227pb5f21 t13 io228nb5f21 ab10 io228pb5f21 ab11 io229nb5f21 ad9 624-pin ccga/lga rtax2000s/sl function pin number io229pb5f21 ad10 io230nb5f21 v11 io233nb5f21 ad7 io233pb5f21 ad8 io234nb5f21 v9 io234pb5f21 v10 io236nb5f22 ac9 io238nb5f22 w8 io238pb5f22 w9 io239nb5f22 ae4 io239pb5f22 ae5 io240nb5f22 ab9 io242nb5f22 aa9 io242pb5f22 y9 io243nb5f22 ad5 io243pb5f22 ad6 io244nb5f22 u8 io246nb5f23 ab8 io246pb5f23 ac8 io247nb5f23 ab7 io247pb5f23 ac7 io250nb5f23 aa8 io250pb5f23 y8 io251nb5f23 v8 io251pb5f23 v7 io252nb5f23 y7 io252pb5f23 w7 io253nb5f23 ac5 io253pb5f23 ac6 io254nb5f23 y6 io254pb5f23 w6 io256nb5f23 ab6 io256pb5f23 aa6 bank 6 io257nb6f24 y3 io257pb6f24 aa3 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-42 v5.4 io258nb6f24 v3 io258pb6f24 w3 io259nb6f24 aa2 io259pb6f24 ab2 io260nb6f24 v6 io260pb6f24 w4 io262nb6f24 u4 io262pb6f24 v4 io263nb6f24 y5 io263pb6f24 w5 io268nb6f25 u6 io268pb6f25 u5 io269pb6f25 u3 io272nb6f25 t2 io272pb6f25 u2 io273nb6f25 w2 io273pb6f25 y2 io274nb6f25 r6 io274pb6f25 t6 io275nb6f25 t7 io275pb6f25 u7 io277nb6f25 v2 io278nb6f26 r4 io278pb6f26 t4 io279pb6f26 r3 io280nb6f26 r5 io281nb6f26 aa1 io281pb6f26 ab1 io284nb6f26 r8 io284pb6f26 t8 io285nb6f26 w1 io285pb6f26 y1 io286nb6f26 p2 io286pb6f26 r2 io287nb6f26 t1 io287pb6f26 u1 624-pin ccga/lga rtax2000s/sl function pin number io288nb6f26 p5 io290nb6f27 p6 io291nb6f27 p1 io291pb6f27 r1 io292nb6f27 p7 io292pb6f27 r7 io293nb6f27 m1 io293pb6f27 n1 io294nb6f27 p8 io296nb6f27 n3 io296pb6f27 p3 io298nb6f27 n4 io298pb6f27 p4 io299nb6f27 m2 io299pb6f27 n2 bank 7 io300nb7f28 p9 io300pb7f28 n6 io302nb7f28 m6 io304nb7f28 n8 io304pb7f28 n7 io308nb7f28 m4 io309nb7f28 l3 io309pb7f28 m3 io310nb7f29 n10 io310pb7f29 n9 io311nb7f29 k1 io311pb7f29 l1 io313nb7f29 m5 io316nb7f29 l6 io316pb7f29 l5 io317nb7f29 k2 io317pb7f29 l2 io318nb7f29 k4 io318pb7f29 l4 io320nb7f29 j3 624-pin ccga/lga rtax2000s/sl function pin number io321nb7f30 j2 io321pb7f30 j1 io323nb7f30 l7 io323pb7f30 m7 io324nb7f30 m9 io324pb7f30 m8 io327nb7f30 f1 io327pb7f30 g1 io328nb7f30 k7 io328pb7f30 k6 io329nb7f30 d1 io329pb7f30 e1 io331pb7f30 g2 io332nb7f31 h3 io332pb7f31 h2 io333nb7f31 e2 io333pb7f31 f2 io334nb7f31 h4 io334pb7f31 j4 io335nb7f31 h5 io335pb7f31 h6 io337nb7f31 d2 io338nb7f31 j6 io338pb7f31 j5 io339nb7f31 f3 io339pb7f31 e3 io340nb7f31 g4 io340pb7f31 g3 io341nb7f31 k8 io341pb7f31 l8 dedicated i/o gnd k5 gnd a18 gnd a2 gnd a24 gnd a25 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-43 gnd a8 gnd aa10 gnd aa16 gnd aa18 gnd aa21 gnd aa5 gnd ab22 gnd ab4 gnd ac10 gnd ac16 gnd ac23 gnd ac3 gnd ad1 gnd ad2 gnd ad24 gnd ad25 gnd ae1 gnd ae18 gnd ae2 gnd ae24 gnd ae25 gnd ae8 gnd b1 gnd b2 gnd b24 gnd b25 gnd c10 gnd c16 gnd c23 gnd c3 gnd d22 gnd d4 gnd e10 gnd e16 gnd e21 gnd e5 624-pin ccga/lga rtax2000s/sl function pin number gnd e8 gnd h1 gnd h21 gnd h25 gnd k21 gnd k23 gnd k3 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd t21 gnd t23 gnd t3 gnd t5 624-pin ccga/lga rtax2000s/sl function pin number gnd v1 gnd v25 gnd v5 nc aa12 nc aa14 nc e12 nc e14 nc f12 nc f14 nc h12 nc h14 nc j12 nc j14 nc u12 nc u14 nc v12 nc v14 nc y12 nc y14 pra f13 prb a13 prc ab12 prd ae13 tck f5 tdi c5 tdo f6 tms d6 trst e6 v cca ab20 v cca f22 v cca f4 v cca j17 v cca j9 v cca k10 v cca k11 v cca k15 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-44 v5.4 v cca k16 v cca l10 v cca l16 v cca r10 v cca r16 v cca t10 v cca t11 v cca t15 v cca t16 v cca u17 v cca u9 v cca y4 v ccda a12 v ccda a14 v ccda aa13 v ccda aa15 v ccda aa20 v ccda aa7 v ccda ab13 v ccda ac11 v ccda ad11 v ccda ad4 v ccda ae12 v ccda ae17 v ccda b15 v ccda c15 v ccda c6 v ccda d13 v ccda e13 v ccda e19 v ccda f21 v ccda g10 v ccda g5 v ccda n21 v ccda n5 v ccda w21 624-pin ccga/lga rtax2000s/sl function pin number v cci b0 a3 v cci b0 b3 v cci b0 c4 v cci b0 d5 v cci b0 j10 v cci b0 j11 v cci b0 k12 v cci b1 a23 v cci b1 b23 v cci b1 c22 v cci b1 d21 v cci b1 j15 v cci b1 j16 v cci b1 k14 v cci b2 c24 v cci b2 c25 v cci b2 d23 v cci b2 e22 v cci b2 k17 v cci b2 l17 v cci b2 m16 v cci b3 aa22 v cci b3 ab23 v cci b3 ac24 v cci b3 ac25 v cci b3 p16 v cci b3 r17 v cci b3 t17 v cci b4 ab21 v cci b4 ac22 v cci b4 ad23 v cci b4 ae23 v cci b4 t14 v cci b4 u15 v cci b4 u16 v cci b5 ab5 624-pin ccga/lga rtax2000s/sl function pin number v cci b5 ac4 v cci b5 ad3 v cci b5 ae3 v cci b5 t12 v cci b5 u10 v cci b5 u11 v cci b6 aa4 v cci b6 ab3 v cci b6 ac1 v cci b6 ac2 v cci b6 p10 v cci b6 r9 v cci b6 t9 v cci b7 c1 v cci b7 c2 v cci b7 d3 v cci b7 e4 v cci b7 k9 v cci b7 l9 v cci b7 m10 v pump e20 624-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-45 1152-pin ccga/lga note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . figure 3-5 ? 1152-pin ccga/lga (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ap an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a
rtax-s/sl radtolerant fpgas 3-46 v5.4 1152-pin ccga/lga rtax2000s/sl function pin number bank 0 io00nb0f0 d6 io00pb0f0 c6 io01nb0f0 h10 io01pb0f0 h9 io02nb0f0 f8 io02pb0f0 g8 io03nb0f0 a6 io03pb0f0 b6 io04nb0f0 c7 io04pb0f0 d7 io05nb0f0 k10 io05pb0f0 j10 io06nb0f0 f9 io06pb0f0 g9 io07nb0f0 f10 io07pb0f0 g10 io08nb0f0 e9 io08pb0f0 e8 io09nb0f0 j11 io09pb0f0 k11 io10nb0f0 c8 io10pb0f0 d8 io11nb0f0 k12 io11pb0f0 j12 io12nb0f1 g11 io12pb0f1 h11 io13nb0f1 g12 io13pb0f1 h12 io14nb0f1 a7 io14pb0f1 b7 io15nb0f1 h13 io15pb0f1 j13 io16nb0f1 c9 io16pb0f1 d9 io17nb0f1 f12 io17pb0f1 f11 io18nb0f1 e11 io18pb0f1 e10 io19nb0f1 f13 io19pb0f1 g13 io20nb0f1 a10 io20pb0f1 a9 io21nb0f1 k14 io21pb0f1 k13 io22nb0f2 b11 io22pb0f2 b10 io23nb0f2 c12 io23pb0f2 c11 io24nb0f2 a12 io24pb0f2 a11 io25nb0f2 h14 io25pb0f2 j14 io26nb0f2 d13 io26pb0f2 d12 io27nb0f2 f14 io27pb0f2 g14 io28nb0f2 e14 io28pb0f2 e13 io29nb0f2 b13 io29pb0f2 b12 io30nb0f2 c14 io30pb0f2 c13 io31nb0f2 h15 io31pb0f2 j15 io32nb0f2 a14 io32pb0f2 b14 io33nb0f2 k15 io33pb0f2 l15 io34nb0f3 d15 io34pb0f3 d14 io35nb0f3 a15 io35pb0f3 b15 io36nb0f3 b16 1152-pin ccga/lga rtax2000s/sl function pin number io36pb0f3 a16 io37nb0f3 g16 io37pb0f3 g15 io38nb0f3 d16 io38pb0f3 c16 io39nb0f3 k16 io39pb0f3 l16 io40nb0f3 d17 io40pb0f3 c17 io41nb0f3/hclkan e16 io41pb0f3/hclkap f16 io42nb0f3/hclkbn g17 io42pb0f3/hclkbp f17 bank 1 io43nb1f4/hclkcn g19 io43pb1f4/hclkcp g18 io44nb1f4/hclkdn e19 io44pb1f4/hclkdp f19 io45nb1f4 c18 io45pb1f4 d18 io46nb1f4 a18 io46pb1f4 b18 io47nb1f4 k19 io47pb1f4 l19 io48nb1f4 c19 io48pb1f4 d19 io49nb1f4 k20 io49pb1f4 l20 io50nb1f4 a19 io50pb1f4 b19 io51nb1f4 h20 io51pb1f4 j20 io52nb1f4 b20 io52pb1f4 a20 io53nb1f4 f20 io53pb1f4 e20 io54nb1f5 b21 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-47 io54pb1f5 a21 io55nb1f5 k21 io55pb1f5 j21 io56nb1f5 d21 io56pb1f5 c21 io57nb1f5 g22 io57pb1f5 g21 io58nb1f5 e22 io58pb1f5 e21 io59nb1f5 d22 io59pb1f5 c22 io60nb1f5 b23 io60pb1f5 a23 io61nb1f5 h22 io61pb1f5 h21 io62nb1f5 c24 io62pb1f5 c23 io63nb1f5 f23 io63pb1f5 f22 io64nb1f6 b24 io64pb1f6 a24 io65nb1f6 j22 io65pb1f6 k22 io66nb1f6 b25 io66pb1f6 a25 io67nb1f6 k23 io67pb1f6 j23 io68nb1f6 f24 io68pb1f6 e24 io69nb1f6 c27 io69pb1f6 c26 io70nb1f6 h24 io70pb1f6 g24 io71nb1f6 h23 io71pb1f6 g23 io72nb1f6 b28 io72pb1f6 a28 1152-pin ccga/lga rtax2000s/sl function pin number io73nb1f6 e26 io73pb1f6 e25 io74nb1f6 f26 io74pb1f6 f25 io75nb1f6 k25 io75pb1f6 k24 io76nb1f7 d27 io76pb1f7 d26 io77nb1f7 b29 io77pb1f7 a29 io78nb1f7 d28 io78pb1f7 c28 io79nb1f7 h25 io79pb1f7 g25 io80nb1f7 f27 io80pb1f7 e27 io81nb1f7 j25 io81pb1f7 j24 io82nb1f7 d29 io82pb1f7 c29 io83nb1f7 h26 io83pb1f7 g26 io84nb1f7 f28 io84pb1f7 e28 io85nb1f7 h27 io85pb1f7 g27 bank 2 io86nb2f8 j28 io86pb2f8 j27 io87nb2f8 m25 io87pb2f8 l25 io88nb2f8 l26 io88pb2f8 k26 io89nb2f8 g31 io89pb2f8 f31 io90nb2f8 h29 io90pb2f8 g29 1152-pin ccga/lga rtax2000s/sl function pin number io91nb2f8 k28 io91pb2f8 k27 io92nb2f8 j30 io92pb2f8 h30 io93nb2f8 l28 io93pb2f8 l27 io94nb2f8 k29 io94pb2f8 j29 io95nb2f8 k31 io95pb2f8 j31 io96nb2f9 j32 io96pb2f9 h32 io97nb2f9 m27 io97pb2f9 m26 io98nb2f9 l30 io98pb2f9 k30 io99nb2f9 n25 io99pb2f9 n26 io100nb2f9 m29 io100pb2f9 l29 io101nb2f9 l33 io101pb2f9 l32 io102nb2f9 k34 io102pb2f9 k33 io103nb2f9 n28 io103pb2f9 m28 io104nb2f9 m34 io104pb2f9 l34 io105nb2f9 p27 io105pb2f9 n27 io106nb2f9 m32 io106pb2f9 m31 io107nb2f10 p25 io107pb2f10 p26 io108nb2f10 n33 io108pb2f10 m33 io109nb2f10 p29 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-48 v5.4 io109pb2f10 n29 io110nb2f10 p30 io110pb2f10 n30 io111nb2f10 r24 io111pb2f10 r25 io112nb2f10 p31 io112pb2f10 n31 io113nb2f10 r28 io113pb2f10 p28 io114nb2f10 p32 io114pb2f10 n32 io115nb2f10 r30 io115pb2f10 r29 io116nb2f10 p34 io116pb2f10 p33 io117nb2f10 r27 io117pb2f10 r26 io118nb2f11 r34 io118pb2f11 r33 io119nb2f11 t24 io119pb2f11 t25 io120nb2f11 t33 io120pb2f11 t34 io121nb2f11 t27 io121pb2f11 t26 io122nb2f11 t30 io122pb2f11 t29 io123nb2f11 u28 io123pb2f11 t28 io124nb2f11 t31 io124pb2f11 t32 io125nb2f11 u24 io125pb2f11 u25 io126nb2f11 u33 io126pb2f11 u34 io127nb2f11 u26 io127pb2f11 u27 1152-pin ccga/lga rtax2000s/sl function pin number io128nb2f11 u31 io128pb2f11 u32 bank 3 io129nb3f12 v29 io129pb3f12 u29 io130nb3f12 v31 io130pb3f12 v32 io131nb3f12 v24 io131pb3f12 v25 io132nb3f12 w28 io132pb3f12 v28 io133nb3f12 w26 io133pb3f12 v26 io134nb3f12 w33 io134pb3f12 v33 io135nb3f12 w25 io135pb3f12 w24 io136nb3f12 w31 io136pb3f12 w32 io137nb3f12 y30 io137pb3f12 w30 io138nb3f12 y29 io138pb3f12 w29 io139nb3f13 y27 io139pb3f13 w27 io140nb3f13 aa33 io140pb3f13 y33 io141nb3f13 y25 io141pb3f13 y24 io142nb3f13 aa31 io142pb3f13 y31 io143nb3f13 aa28 io143pb3f13 y28 io144nb3f13 aa34 io144pb3f13 y34 io145nb3f13 aa26 io145pb3f13 y26 1152-pin ccga/lga rtax2000s/sl function pin number io146nb3f13 aa29 io146pb3f13 aa30 io147nb3f13 ab30 io147pb3f13 ab29 io148nb3f13 ab32 io148pb3f13 aa32 io149nb3f13 ab27 io149pb3f13 aa27 io150nb3f14 ac31 io150pb3f14 ab31 io151nb3f14 ad33 io151pb3f14 ac33 io152nb3f14 ac28 io152pb3f14 ab28 io153nb3f14 ab25 io153pb3f14 aa25 io154nb3f14 ad32 io154pb3f14 ac32 io155nb3f14 ad29 io155pb3f14 ac29 io156nb3f14 ae30 io156pb3f14 ad30 io157nb3f14 ac26 io157pb3f14 ab26 io158nb3f14 ah33 io158pb3f14 ag33 io159nb3f14 ad27 io159pb3f14 ac27 io160nb3f14 ag32 io160pb3f14 af32 io161nb3f15 ag31 io161pb3f15 af31 io162nb3f15 af29 io162pb3f15 ae29 io163nb3f15 ae28 io163pb3f15 ad28 io164nb3f15 ag30 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-49 io164pb3f15 af30 io165nb3f15 ae26 io165pb3f15 ad26 io166nb3f15 aj30 io166pb3f15 ah30 io167nb3f15 ag28 io167pb3f15 af28 io168nb3f15 af27 io168pb3f15 ae27 io169nb3f15 ah29 io169pb3f15 ag29 io170nb3f15 ad25 io170pb3f15 ac25 bank 4 io171nb4f16 ap29 io171pb4f16 an29 io172nb4f16 ah26 io172pb4f16 ah27 io173nb4f16 aj27 io173pb4f16 aj28 io174nb4f16 al27 io174pb4f16 al28 io175nb4f16 am28 io175pb4f16 am29 io176nb4f16 ag25 io176pb4f16 ag26 io177nb4f16 ak26 io177pb4f16 ak27 io178nb4f16 af25 io178pb4f16 ae25 io179nb4f16 ap28 io179pb4f16 an28 io180nb4f16 aj25 io180pb4f16 aj26 io181nb4f17 am26 io181pb4f17 am27 io182nb4f17 af24 1152-pin ccga/lga rtax2000s/sl function pin number io182pb4f17 ae24 io183nb4f17 ah24 io183pb4f17 ah25 io184nb4f17 ag23 io184pb4f17 ag24 io185nb4f17 al25 io185pb4f17 al26 io186nb4f17 ap25 io186pb4f17 ap26 io187nb4f17 ak24 io187pb4f17 ak25 io188nb4f17 af23 io188pb4f17 ae23 io189nb4f17 an24 io189pb4f17 am24 io190nb4f17 ah22 io190pb4f17 ah23 io191nb4f17 aj23 io191pb4f17 aj24 io192nb4f17 ag21 io192pb4f17 ag22 io193nb4f18 ap23 io193pb4f18 ap24 io194nb4f18 an22 io194pb4f18 an23 io195nb4f18 am23 io195pb4f18 al23 io196nb4f18 af21 io196pb4f18 af22 io197nb4f18 al22 io197pb4f18 am22 io198nb4f18 ae21 io198pb4f18 ae22 io199nb4f18 aj21 io199pb4f18 aj22 io200nb4f18 ak21 io200pb4f18 ak22 1152-pin ccga/lga rtax2000s/sl function pin number io201nb4f18 am21 io201pb4f18 al21 io202nb4f18 ae20 io202pb4f18 ad20 io203nb4f19 an21 io203pb4f19 ap21 io204nb4f19 ap20 io204pb4f19 an20 io205nb4f19 an19 io205pb4f19 ap19 io206nb4f19 ag20 io206pb4f19 af20 io207nb4f19 al19 io207pb4f19 al20 io208nb4f19 ag19 io208pb4f19 af19 io209nb4f19 an18 io209pb4f19 ap18 io210nb4f19 ae19 io210pb4f19 ad19 io211nb4f19 al18 io211pb4f19 am18 io212nb4f19/clken aj20 io212pb4f19/clkep ak20 io213nb4f19/clkfn aj18 io213pb4f19/clkfp aj19 bank 5 io214nb5f20/clkgn aj16 io214pb5f20/clkgp aj17 io215nb5f20/clkhn aj15 io215pb5f20/clkhp ak15 io216nb5f20 ad16 io216pb5f20 ae17 io217nb5f20 am17 io217pb5f20 al17 io218nb5f20 ag16 io218pb5f20 af16 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-50 v5.4 io219nb5f20 am16 io219pb5f20 al16 io220nb5f20 ap16 io220pb5f20 an16 io221nb5f20 an15 io221pb5f20 ap15 io222nb5f20 ad15 io222pb5f20 ae16 io223nb5f21 al14 io223pb5f21 al15 io224nb5f21 an14 io224pb5f21 ap14 io225nb5f21 ak13 io225pb5f21 ak14 io226nb5f21 ae15 io226pb5f21 af15 io227nb5f21 ag14 io227pb5f21 ag15 io228nb5f21 aj13 io228pb5f21 aj14 io229nb5f21 am13 io229pb5f21 am14 io230nb5f21 ae14 io230pb5f21 af14 io231nb5f21 an12 io231pb5f21 ap12 io232nb5f21 ag13 io232pb5f21 ah13 io233nb5f21 al12 io233pb5f21 al13 io234nb5f21 ae13 io234pb5f21 af13 io235nb5f22 an11 io235pb5f22 ap11 io236nb5f22 am11 io236pb5f22 am12 io237nb5f22 aj11 1152-pin ccga/lga rtax2000s/sl function pin number io237pb5f22 aj12 io238nb5f22 ah11 io238pb5f22 ah12 io239nb5f22 ak10 io239pb5f22 ak11 io240nb5f22 ae12 io240pb5f22 af12 io241nb5f22 an10 io241pb5f22 ap10 io242nb5f22 ag11 io242pb5f22 ag12 io243nb5f22 al9 io243pb5f22 al10 io244nb5f22 am8 io244pb5f22 am9 io245nb5f23 ah10 io245pb5f23 aj10 io246nb5f23 af10 io246pb5f23 af11 io247nb5f23 aj9 io247pb5f23 ak9 io248nb5f23 an7 io248pb5f23 ap7 io249nb5f23 al7 io249pb5f23 al8 io250nb5f23 ae10 io250pb5f23 ae11 io251nb5f23 ak8 io251pb5f23 aj8 io252nb5f23 ah8 io252pb5f23 ah9 io253nb5f23 an6 io253pb5f23 ap6 io254nb5f23 ag9 io254pb5f23 ag10 io255nb5f23 aj7 io255pb5f23 ak7 1152-pin ccga/lga rtax2000s/sl function pin number io256nb5f23 al6 io256pb5f23 am6 bank 6 io257nb6f24 ag6 io257pb6f24 ah6 io258nb6f24 ad9 io258pb6f24 ae9 io259nb6f24 af7 io259pb6f24 ag7 io260nb6f24 ah3 io260pb6f24 ah4 io261nb6f24 ah5 io261pb6f24 aj5 io262nb6f24 ae6 io262pb6f24 af6 io263nb6f24 af5 io263pb6f24 ag5 io264nb6f24 ad8 io264pb6f24 ae8 io265nb6f24 af3 io265pb6f24 ag3 io266nb6f24 ac10 io266pb6f24 ad10 io267nb6f25 ad7 io267pb6f25 ae7 io268nb6f25 ad5 io268pb6f25 ae5 io269nb6f25 ae4 io269pb6f25 af4 io270nb6f25 ab9 io270pb6f25 ac9 io271nb6f25 ac6 io271pb6f25 ad6 io272nb6f25 ab8 io272pb6f25 ac8 io273nb6f25 ae1 io273pb6f25 ae2 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-51 io274nb6f25 aa10 io274pb6f25 ab10 io275nb6f25 ab7 io275pb6f25 ac7 io276nb6f25 ad1 io276pb6f25 ad2 io277nb6f25 ac4 io277pb6f25 ac3 io278nb6f26 aa8 io278pb6f26 aa9 io279nb6f26 ab5 io279pb6f26 ab6 io280nb6f26 y10 io280pb6f26 y11 io281nb6f26 ab3 io281pb6f26 ab4 io282nb6f26 y7 io282pb6f26 aa7 io283nb6f26 ac2 io283pb6f26 ac1 io284nb6f26 y9 io284pb6f26 y8 io285nb6f26 aa5 io285pb6f26 aa6 io286nb6f26 w10 io286pb6f26 w11 io287nb6f26 aa3 io287pb6f26 aa4 io288nb6f26 w9 io288pb6f26 w8 io289nb6f27 aa1 io289pb6f27 aa2 io290nb6f27 w6 io290pb6f27 y6 io291nb6f27 w5 io291pb6f27 y5 io292nb6f27 v7 1152-pin ccga/lga rtax2000s/sl function pin number io292pb6f27 w7 io293nb6f27 w4 io293pb6f27 y4 io294nb6f27 v10 io294pb6f27 v11 io295nb6f27 y1 io295pb6f27 y2 io296nb6f27 w1 io296pb6f27 w2 io297nb6f27 v1 io297pb6f27 v2 io298nb6f27 v9 io298pb6f27 v8 io299nb6f27 u4 io299pb6f27 v4 bank 7 io300nb7f28 u10 io300pb7f28 u11 io301nb7f28 u2 io301pb7f28 u1 io302nb7f28 u6 io302pb7f28 u7 io303nb7f28 t3 io303pb7f28 u3 io304nb7f28 u9 io304pb7f28 u8 io305nb7f28 r2 io305pb7f28 r1 io306nb7f28 r4 io306pb7f28 t4 io307nb7f28 r5 io307pb7f28 t5 io308nb7f28 t11 io308pb7f28 t10 io309nb7f28 t6 io309pb7f28 t7 io310nb7f29 t9 1152-pin ccga/lga rtax2000s/sl function pin number io310pb7f29 t8 io311nb7f29 n3 io311pb7f29 p3 io312nb7f29 p7 io312pb7f29 r7 io313nb7f29 p6 io313pb7f29 r6 io314nb7f29 m2 io314pb7f29 n2 io315nb7f29 n4 io315pb7f29 p4 io316nb7f29 r9 io316pb7f29 r8 io317nb7f29 n5 io317pb7f29 p5 io318nb7f29 r10 io318pb7f29 r11 io319nb7f29 l2 io319pb7f29 l1 io320nb7f29 n8 io320pb7f29 p8 io321nb7f30 m6 io321pb7f30 n6 io322nb7f30 p10 io322pb7f30 p9 io323nb7f30 l3 io323pb7f30 m3 io324nb7f30 m7 io324pb7f30 n7 io325nb7f30 k2 io325pb7f30 k1 io326nb7f30 g2 io326pb7f30 h2 io327nb7f30 l6 io327pb7f30 l5 io328nb7f30 n10 io328pb7f30 n9 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-52 v5.4 io329nb7f30 j4 io329pb7f30 k4 io330nb7f30 j5 io330pb7f30 k5 io331nb7f30 m10 io331pb7f30 m9 io332nb7f31 l8 io332pb7f31 m8 io333nb7f31 f2 io333pb7f31 f1 io334nb7f31 j6 io334pb7f31 k6 io335nb7f31 h4 io335pb7f31 h3 io336nb7f31 k7 io336pb7f31 l7 io337nb7f31 g4 io337pb7f31 g3 io338nb7f31 k9 io338pb7f31 l9 io339nb7f31 h6 io339pb7f31 h5 io340nb7f31 h7 io340pb7f31 j7 io341nb7f31 j8 io341pb7f31 k8 dedicated i/o gnd a13 gnd a2 gnd a22 gnd a27 gnd a3 gnd a31 gnd a32 gnd a33 gnd a4 gnd a8 1152-pin ccga/lga rtax2000s/sl function pin number gnd aa14 gnd aa15 gnd aa16 gnd aa17 gnd aa18 gnd aa19 gnd aa20 gnd aa21 gnd ab1 gnd ab13 gnd ab22 gnd ab34 gnd ac12 gnd ac23 gnd ac30 gnd ac5 gnd ad11 gnd ad24 gnd ad31 gnd ad4 gnd ae3 gnd ae32 gnd af2 gnd af33 gnd ag1 gnd ag27 gnd ag34 gnd ag8 gnd ah28 gnd ah7 gnd aj29 gnd aj6 gnd ak12 gnd ak17 gnd ak18 gnd ak23 gnd ak30 1152-pin ccga/lga rtax2000s/sl function pin number gnd ak5 gnd al1 gnd al11 gnd al2 gnd al24 gnd al3 gnd al31 gnd al32 gnd al33 gnd al34 gnd al4 gnd am1 gnd am10 gnd am15 gnd am2 gnd am20 gnd am25 gnd am3 gnd am31 gnd am32 gnd am33 gnd am34 gnd am4 gnd an1 gnd an2 gnd an26 gnd an3 gnd an31 gnd an32 gnd an33 gnd an34 gnd an4 gnd an9 gnd ap13 gnd ap2 gnd ap22 gnd ap27 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-53 gnd ap3 gnd ap31 gnd ap32 gnd ap33 gnd ap4 gnd ap8 gnd b1 gnd b2 gnd b26 gnd b3 gnd b31 gnd b32 gnd b33 gnd b34 gnd b4 gnd b9 gnd c1 gnd c10 gnd c15 gnd c2 gnd c20 gnd c25 gnd c3 gnd c31 gnd c32 gnd c33 gnd c34 gnd c4 gnd d1 gnd d11 gnd d2 gnd d24 gnd d3 gnd d31 gnd d32 gnd d33 gnd d34 1152-pin ccga/lga rtax2000s/sl function pin number gnd d4 gnd e12 gnd e17 gnd e18 gnd e23 gnd e30 gnd e5 gnd f29 gnd f30 gnd f6 gnd g28 gnd g6 gnd g7 gnd h1 gnd h34 gnd j2 gnd j33 gnd k3 gnd k32 gnd l11 gnd l24 gnd l31 gnd l4 gnd m12 gnd m23 gnd m30 gnd m5 gnd n1 gnd n13 gnd n22 gnd n34 gnd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 1152-pin ccga/lga rtax2000s/sl function pin number gnd p20 gnd p21 gnd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r20 gnd r21 gnd r3 gnd r32 gnd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t20 gnd t21 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd u20 gnd u21 gnd u30 gnd u5 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v20 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-54 v5.4 gnd v21 gnd v30 gnd v5 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 gnd w21 gnd y14 gnd y15 gnd y16 gnd y17 gnd y18 gnd y19 gnd y20 gnd y21 gnd y3 gnd y32 nc a17 nc a26 nc ab2 nc ab33 nc ac34 nc ad17 nc ad3 nc ad34 nc ae18 nc ae31 nc ae33 nc ae34 nc af1 nc af17 nc af18 nc af34 1152-pin ccga/lga rtax2000s/sl function pin number nc ag2 nc ag4 nc ah1 nc ah16 nc ah19 nc ah2 nc ah31 nc ah32 nc ah34 nc aj1 nc aj2 nc aj3 nc aj31 nc aj32 nc aj33 nc aj34 nc aj4 nc ak16 nc ak19 nc al29 nc am19 nc am7 nc an13 nc an17 nc an25 nc an27 nc an8 nc ap17 nc ap9 nc b17 nc b22 nc b27 nc b8 nc d10 nc d20 nc d23 nc d25 1152-pin ccga/lga rtax2000s/sl function pin number nc f3 nc f32 nc f33 nc f34 nc f4 nc g1 nc g32 nc g33 nc g34 nc h16 nc h19 nc h31 nc h33 nc j1 nc j16 nc j19 nc j3 nc j34 nc k17 nc k18 nc l17 nc l18 nc m1 nc m4 nc p1 nc p2 nc r31 nc t1 nc t2 nc v3 nc v34 nc w3 nc w34 pra j17 prb f18 prc ad18 prd ah18 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-55 tck j9 tdi f7 tdo l10 tms h8 trst e6 v cca aa13 v cca aa22 v cca ab14 v cca ab15 v cca ab16 v cca ab17 v cca ab18 v cca ab19 v cca ab20 v cca ab21 v cca af8 v cca ak28 v cca g30 v cca g5 v cca n14 v cca n15 v cca n16 v cca n17 v cca n18 v cca n19 v cca n20 v cca n21 v cca p13 v cca p22 v cca r13 v cca r22 v cca t13 v cca t22 v cca u13 v cca u22 v cca v13 v cca v22 1152-pin ccga/lga rtax2000s/sl function pin number v cca w13 v cca w22 v cca y13 v cca y22 v ccda af26 v ccda af9 v ccda ag17 v ccda ag18 v ccda ah14 v ccda ah15 v ccda ah17 v ccda ah20 v ccda ah21 v ccda ak29 v ccda ak6 v ccda e15 v ccda e29 v ccda e7 v ccda f15 v ccda f21 v ccda f5 v ccda g20 v ccda h17 v ccda h18 v ccda h28 v ccda j18 v ccda v27 v ccda v6 v cci b0 a5 v cci b0 b5 v cci b0 c5 v cci b0 d5 v cci b0 l12 v cci b0 l13 v cci b0 l14 v cci b0 m13 v cci b0 m14 1152-pin ccga/lga rtax2000s/sl function pin number v cci b0 m15 v cci b0 m16 v cci b0 m17 v cci b1 a30 v cci b1 b30 v cci b1 c30 v cci b1 d30 v cci b1 l21 v cci b1 l22 v cci b1 l23 v cci b1 m18 v cci b1 m19 v cci b1 m20 v cci b1 m21 v cci b1 m22 v cci b2 e31 v cci b2 e32 v cci b2 e33 v cci b2 e34 v cci b2 m24 v cci b2 n23 v cci b2 n24 v cci b2 p23 v cci b2 p24 v cci b2 r23 v cci b2 t23 v cci b2 u23 v cci b3 aa23 v cci b3 aa24 v cci b3 ab23 v cci b3 ab24 v cci b3 ac24 v cci b3 ak31 v cci b3 ak32 v cci b3 ak33 v cci b3 ak34 v cci b3 v23 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-56 v5.4 v cci b3 w23 v cci b3 y23 v cci b4 ac18 v cci b4 ac19 v cci b4 ac20 v cci b4 ac21 v cci b4 ac22 v cci b4 ad21 v cci b4 ad22 v cci b4 ad23 v cci b4 al30 v cci b4 am30 v cci b4 an30 v cci b4 ap30 v cci b5 ac13 v cci b5 ac14 v cci b5 ac15 1152-pin ccga/lga rtax2000s/sl function pin number v cci b5 ac16 v cci b5 ac17 v cci b5 ad12 v cci b5 ad13 v cci b5 ad14 v cci b5 al5 v cci b5 am5 v cci b5 an5 v cci b5 ap5 v cci b6 aa11 v cci b6 aa12 v cci b6 ab11 v cci b6 ab12 v cci b6 ac11 v cci b6 ak1 v cci b6 ak2 v cci b6 ak3 1152-pin ccga/lga rtax2000s/sl function pin number v cci b6 ak4 v cci b6 v12 v cci b6 w12 v cci b6 y12 v cci b7 e1 v cci b7 e2 v cci b7 e3 v cci b7 e4 v cci b7 m11 v cci b7 n11 v cci b7 n12 v cci b7 p11 v cci b7 p12 v cci b7 r12 v cci b7 t12 v cci b7 u12 v pump j26 1152-pin ccga/lga rtax2000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-57 1272-pin ccga/lga note for package manufacturing and environmental in formation, visit the resource center at http://www.actel.com/products/ solutions/package/docs.aspx . figure 3-6 ? 1272-pin ccga/lga (bottom view) 3 6 at ar ap an am al ak a j ah a g af ae ad a c ab aa y w v u t r p n m l k j h g f e d c b a 35 34 33 32 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 1 6 15 14 13 12 11 10 9 8 7 6 54 1 32
rtax-s/sl radtolerant fpgas 3-58 v5.4 1272-pin ccga/lga rtax4000s/sl function pin number bank 0 io00nb0f0 e9 io00pb0f0 d9 io01nb0f0 d8 io01pb0f0 d7 io02nb0f0 j10 io02pb0f0 j9 io03nb0f0 e7 io03pb0f0 e8 io04nb0f0 f9 io04pb0f0 g9 io05nb0f0 b7 io05pb0f0 b6 io06nb0f0 l13 io06pb0f0 l12 io07nb0f0 c7 io07pb0f0 c6 io08nb0f0 f10 io08pb0f0 g10 io09nb0f0 d10 io09pb0f0 e10 io10nb0f0 h11 io10pb0f0 h10 io11nb0f0 a5 io11pb0f0 a4 io12nb0f1 d6 io12pb0f1 d5 io13nb0f1 a7 io13pb0f1 a6 io14nb0f1 j12 io14pb0f1 j11 io15nb0f1 d12 io15pb0f1 d11 io16nb0f1 f12 io16pb0f1 g12 io17nb0f1 e12 io17pb0f1 e11 io18nb0f1 k13 io18pb0f1 k12 io19nb0f1 b4 io19pb0f1 c4 io20nb0f1 h13 io20pb0f1 h12 io21nb0f2 c13 io21pb0f2 c12 io22nb0f2 m14 io22pb0f2 m13 io23nb0f2 b10 io23pb0f2 b9 io24nb0f2 j14 io24pb0f2 j13 io25nb0f2 a8 io25pb0f2 a9 io26nb0f2 g13 io26pb0f2 f13 io27nb0f2 d14 io27pb0f2 d13 io28nb0f2 l16 io28pb0f2 l15 io29nb0f2 b13 io29pb0f2 b12 io30nb0f2 c10 io30pb0f2 c9 io31nb0f2 e15 io31pb0f2 e14 io32nb0f2 k15 io32pb0f2 k16 io33nb0f3 a13 io33pb0f3 a12 io34nb0f3 g15 io34pb0f3 f15 io35nb0f3 c15 io35pb0f3 d15 io36nb0f3 j16 1272-pin ccga/lga rtax4000s/sl function pin number io36pb0f3 j15 io37nb0f3 a11 io37pb0f3 a10 io38nb0f3 h15 io38pb0f3 h14 io39nb0f3 b16 io39pb0f3 b15 io40nb0f3 m16 io40pb0f3 m17 io41nb0f3 e16 io41pb0f3 f16 io42nb0f4 h17 io42pb0f4 j17 io43nb0f4 a14 io43pb0f4 a15 io44nb0f4 g16 io44pb0f4 h16 io45nb0f4 a17 io45pb0f4 a16 io46nb0f4 m18 io46pb0f4 m19 io47nb0f4 e18 io47pb0f4 e17 io48nb0f4 g18 io48pb0f4 h18 io49nb0f4 c18 io49pb0f4 b18 io50nb0f4/hclkan j18 io50pb0f4/hclkap k18 io51nb0f4/hclkbn d18 io51pb0f4/hclkbp d17 bank 1 io52nb1f6/hclkcn k19 io52pb1f6/hclkcp j19 io53nb1f6/hclkdn d20 io53pb1f6/hclkdp d19 io54nb1f6 h19 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-59 io54pb1f6 g19 io55nb1f6 b19 io55pb1f6 c19 io56nb1f6 m20 io56pb1f6 m21 io57nb1f6 e20 io57pb1f6 e19 io58nb1f6 h21 io58pb1f6 g21 io59nb1f6 a21 io59pb1f6 a20 io60nb1f7 h20 io60pb1f7 j20 io61nb1f7 a22 io61pb1f7 a23 io62nb1f7 d32 io62pb1f7 d31 io63nb1f7 f21 io63pb1f7 e21 io64nb1f7 j22 io64pb1f7 j21 io65nb1f7 b22 io65pb1f7 b21 io66nb1f7 h23 io66pb1f7 h22 io67nb1f7 d22 io67pb1f7 c22 io68nb1f7 k22 io68pb1f7 k21 io69nb1f7 a27 io69pb1f7 a26 io70nb1f7 f22 io70pb1f7 g22 io71nb1f7 e23 io71pb1f7 e22 io72nb1f8 l22 io72pb1f8 l21 1272-pin ccga/lga rtax4000s/sl function pin number io73nb1f8 a25 io73pb1f8 a24 io74nb1f8 c28 io74pb1f8 c27 io75nb1f8 d24 io75pb1f8 d23 io76nb1f8 j24 io76pb1f8 j23 io77nb1f8 b25 io77pb1f8 b24 io78nb1f8 f24 io78pb1f8 g24 io79nb1f8 a28 io79pb1f8 a29 io80nb1f8 m24 io80pb1f8 m23 io81nb1f8 b28 io81pb1f8 b27 io82nb1f9 h25 io82pb1f9 h24 io83nb1f9 c25 io83pb1f9 c24 io84nb1f9 k25 io84pb1f9 k24 io85nb1f9 a33 io85pb1f9 a32 io86nb1f9 g25 io86pb1f9 f25 io87nb1f9 e26 io87pb1f9 e25 io88nb1f9 j26 io88pb1f9 j25 io89nb1f9 d26 io89pb1f9 d25 io90nb1f9 e31 io90pb1f9 e32 io91nb1f9 a31 1272-pin ccga/lga rtax4000s/sl function pin number io91pb1f9 a30 io92nb1f9 h27 io92pb1f9 h26 io93nb1f9 c33 io93pb1f9 b33 io94nb1f10 g27 io94pb1f10 f27 io95nb1f10 e27 io95pb1f10 d27 io96nb1f10 l24 io96pb1f10 l25 io97nb1f10 c31 io97pb1f10 c30 io98nb1f10 f28 io98pb1f10 g28 io99nb1f10 b31 io99pb1f10 b30 io100nb1f10 j28 io100pb1f10 j27 io101nb1f10 e29 io101pb1f10 e30 io102nb1f10 d28 io102pb1f10 e28 io103nb1f10 d30 io103pb1f10 d29 bank 2 io104nb2f12 l29 io104pb2f12 l28 io105nb2f12 d35 io105pb2f12 d34 io106nb2f12 h33 io106pb2f12 j33 io107nb2f12 f34 io107pb2f12 f33 io108nb2f12 g33 io108pb2f12 g32 io109nb2f12 m28 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-60 v5.4 io109pb2f12 m27 io110nb2f12 k33 io110pb2f12 k32 io111nb2f12 k31 io111pb2f12 k30 io112nb2f13 k34 io112pb2f13 j34 io113nb2f13 n26 io113pb2f13 m26 io114nb2f13 k28 io114pb2f13 k29 io115nb2f13 h32 io115pb2f13 j32 io116nb2f13 g35 io116pb2f13 g34 io117nb2f13 m29 io117pb2f13 m30 io118nb2f13 e33 io118pb2f13 d33 io119nb2f13 m32 io119pb2f13 m31 io120nb2f13 e36 io120pb2f13 d36 io121nb2f14 n28 io121pb2f14 n27 io122nb2f14 l33 io122pb2f14 l32 io123nb2f14 n30 io123pb2f14 n29 io124nb2f14 k35 io124pb2f14 j35 io125nb2f14 p25 io125pb2f14 n25 io126nb2f14 h36 io126pb2f14 g36 io127nb2f14 n32 io127pb2f14 n31 1272-pin ccga/lga rtax4000s/sl function pin number io128nb2f14 n34 io128pb2f14 m34 io129nb2f14 p29 io129pb2f14 p28 io130nb2f15 n33 io130pb2f15 m33 io131nb2f15 r26 io131pb2f15 r25 io132nb2f15 k36 io132pb2f15 j36 io133nb2f15 r29 io133pb2f15 r28 io134nb2f15 n35 io134pb2f15 m35 io135nb2f15 f35 io135pb2f15 f36 io136nb2f15 m36 io136pb2f15 l36 io137nb2f15 t26 io137pb2f15 t25 io138nb2f15 p33 io138pb2f15 p32 io139nb2f16 r31 io139pb2f16 r30 io140nb2f16 p36 io140pb2f16 n36 io141nb2f16 t28 io141pb2f16 t27 io142nb2f16 r35 io142pb2f16 r34 io143nb2f16 t32 io143pb2f16 t31 io144nb2f16 t35 io144pb2f16 t34 io145nb2f16 t30 io145pb2f16 t29 io146nb2f16 r33 1272-pin ccga/lga rtax4000s/sl function pin number io146pb2f16 r32 io147nb2f16 v25 io147pb2f16 u25 io148nb2f17 t36 io148pb2f17 r36 io149nb2f17 u29 io149pb2f17 u28 io150nb2f17 u33 io150pb2f17 t33 io151nb2f17 w25 io151pb2f17 y25 io152nb2f17 v36 io152pb2f17 u36 io153nb2f17 v31 io153pb2f17 v30 io154nb2f17 v32 io154pb2f17 u32 io155nb2f17 v27 io155pb2f17 v28 io156nb2f17 w34 io156pb2f17 v34 bank 3 io157nb3f18 w29 io157pb3f18 v29 io158nb3f18 w35 io158pb3f18 v35 io159nb3f18 w30 io159pb3f18 w31 io160nb3f18 aa36 io160pb3f18 y36 io161nb3f18 w27 io161pb3f18 w28 io162nb3f18 y32 io162pb3f18 w32 io163nb3f18 y28 io163pb3f18 y29 io164nb3f18 ac36 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-61 io164pb3f18 ab36 io165nb3f18 aa26 io165pb3f18 aa25 io166nb3f19 aa33 io166pb3f19 y33 io167nb3f19 aa32 io167pb3f19 aa31 io168nb3f19 aa34 io168pb3f19 aa35 io169nb3f19 aa29 io169pb3f19 aa30 io170nb3f19 ab32 io170pb3f19 ab33 io171nb3f19 ab31 io171pb3f19 ab30 io172nb3f19 ae36 io172pb3f19 ad36 io173nb3f19 aa27 io173pb3f19 aa28 io174nb3f19 ab34 io174pb3f19 ab35 io175nb3f20 al35 io175pb3f20 al36 io176nb3f20 ag36 io176pb3f20 af36 io177nb3f20 ab25 io177pb3f20 ab26 io178nb3f20 ac32 io178pb3f20 ac33 io179nb3f20 ab29 io179pb3f20 ab28 io180nb3f20 aj36 io180pb3f20 ah36 io181nb3f20 ac25 io181pb3f20 ad25 io182nb3f20 ae35 io182pb3f20 ad35 1272-pin ccga/lga rtax4000s/sl function pin number io183nb3f20 ac29 io183pb3f20 ac28 io184nb3f21 ae34 io184pb3f21 ad34 io185nb3f21 ae26 io185pb3f21 ad26 io186nb3f21 ae33 io186pb3f21 ad33 io187nb3f21 ad30 io187pb3f21 ad29 io188nb3f21 ah35 io188pb3f21 ag35 io189nb3f21 ad32 io189pb3f21 ad31 io190nb3f21 ak35 io190pb3f21 ak36 io191nb3f21 ae32 io191pb3f21 ae31 io192nb3f21 an36 io192pb3f21 am36 io193nb3f22 ad27 io193pb3f22 ad28 io194nb3f22 af32 io194pb3f22 af33 io195nb3f22 ae30 io195pb3f22 ae29 io196nb3f22 ak34 io196pb3f22 al34 io197nb3f22 ae28 io197pb3f22 ae27 io198nb3f22 an33 io198pb3f22 am33 io199nb3f22 ah31 io199pb3f22 ah30 io200nb3f22 ah34 io200pb3f22 ag34 io201nb3f22 af29 1272-pin ccga/lga rtax4000s/sl function pin number io201pb3f22 af28 io202nb3f23 ag32 io202pb3f23 ag33 io203nb3f23 ag31 io203pb3f23 ag30 io204nb3f23 al33 io204pb3f23 ak33 io205nb3f23 ak32 io205pb3f23 ak31 io206nb3f23 ah33 io206pb3f23 aj33 io207nb3f23 an34 io207pb3f23 an35 io208nb3f23 ag29 io208pb3f23 ag28 io209nb3f23 aj32 io209pb3f23 ah32 bank 4 io210nb4f24 am28 io210pb4f24 an28 io211nb4f24 an29 io211pb4f24 an30 io212nb4f24 ah27 io212pb4f24 ah28 io213nb4f24 am30 io213pb4f24 am29 io214nb4f24 al28 io214pb4f24 ak28 io215nb4f24 ar30 io215pb4f24 ar31 io216nb4f24 af24 io216pb4f24 af25 io217nb4f24 ap30 io217pb4f24 ap31 io218nb4f24 al27 io218pb4f24 ak27 io219nb4f24 an27 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-62 v5.4 io219pb4f24 am27 io220nb4f25 aj26 io220pb4f25 aj27 io221nb4f25 at32 io221pb4f25 at33 io222nb4f25 an31 io222pb4f25 an32 io223nb4f25 at30 io223pb4f25 at31 io224nb4f25 ah25 io224pb4f25 ah26 io225nb4f25 an25 io225pb4f25 an26 io226nb4f25 al25 io226pb4f25 ak25 io227nb4f25 am25 io227pb4f25 am26 io228nb4f25 ag25 io228pb4f25 ag24 io229nb4f25 ar33 io229pb4f25 ap33 io230nb4f25 aj24 io230pb4f25 aj25 io231nb4f25 at26 io231pb4f25 at27 io232nb4f26 ae23 io232pb4f26 ae24 io233nb4f26 ar27 io233pb4f26 ar28 io234nb4f26 ah23 io234pb4f26 ah24 io235nb4f26 at29 io235pb4f26 at28 io236nb4f26 ak24 io236pb4f26 al24 io237nb4f26 ar24 io237pb4f26 ar25 1272-pin ccga/lga rtax4000s/sl function pin number io238nb4f26 af21 io238pb4f26 af22 io239nb4f26 ap24 io239pb4f26 ap25 io240nb4f26 ap27 io240pb4f26 ap28 io241nb4f26 an23 io241pb4f26 an24 io242nb4f27 ag21 io242pb4f27 ag22 io243nb4f27 am22 io243pb4f27 am23 io244nb4f27 ak22 io244pb4f27 al22 io245nb4f27 at24 io245pb4f27 at25 io246nb4f27 ah21 io246pb4f27 ah22 io247nb4f27 ap22 io247pb4f27 an22 io248nb4f27 aj22 io248pb4f27 aj23 io249nb4f27 ar21 io249pb4f27 ar22 io250nb4f27 ae21 io250pb4f27 ae20 io251nb4f27 am21 io251pb4f27 al21 io252nb4f27 ah20 io252pb4f27 aj20 io253nb4f27 at23 io253pb4f27 at22 io254nb4f28 ak21 io254pb4f28 aj21 io255nb4f28 at20 io255pb4f28 at21 io256nb4f28 ae18 1272-pin ccga/lga rtax4000s/sl function pin number io256pb4f28 ae19 io257nb4f28 am19 io257pb4f28 am20 io258nb4f28 ak19 io258pb4f28 aj19 io259nb4f28 ap19 io259pb4f28 ar19 io260nb4f28/clken ah19 io260pb4f28/clkep ag19 io261nb4f28/clkfn an19 io261pb4f28/clkfp an20 bank 5 io262nb5f30/clkgn ag18 io262pb5f30/clkgp ah18 io263nb5f30/clkhn an17 io263pb5f30/clkhp an18 io264nb5f30 aj18 io264pb5f30 ak18 io265nb5f30 ar18 io265pb5f30 ap18 io266nb5f30 ae17 io266pb5f30 ae16 io267nb5f30 am17 io267pb5f30 am18 io268nb5f30 aj16 io268pb5f30 ak16 io269nb5f30 at16 io269pb5f30 at17 io270nb5f30 af16 io270pb5f30 af15 io271nb5f30 at15 io271pb5f30 at14 io272nb5f31 ah17 io272pb5f31 aj17 io273nb5f31 al16 io273pb5f31 am16 io274nb5f31 ah15 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-63 io274pb5f31 ah16 io275nb5f31 ar15 io275pb5f31 ar16 io276nb5f31 aj14 io276pb5f31 aj15 io277nb5f31 an15 io277pb5f31 ap15 io278nb5f31 ag15 io278pb5f31 ag16 io279nb5f31 at10 io279pb5f31 at11 io280nb5f31 al15 io280pb5f31 ak15 io281nb5f32 am14 io281pb5f32 am15 io282nb5f32 ae13 io282pb5f32 ae14 io283nb5f32 at12 io283pb5f32 at13 io284nb5f32 ap9 io284pb5f32 ap10 io285nb5f32 an13 io285pb5f32 an14 io286nb5f32 an9 io286pb5f32 am9 io287nb5f32 ar12 io287pb5f32 ar13 io288nb5f32 al13 io288pb5f32 ak13 io289nb5f32 at9 io289pb5f32 at8 io290nb5f32 ah13 io290pb5f32 ah14 io291nb5f32 ar9 io291pb5f32 ar10 io292nb5f32 aj12 io292pb5f32 aj13 1272-pin ccga/lga rtax4000s/sl function pin number io293nb5f33 ap12 io293pb5f33 ap13 io294nb5f33 ag13 io294pb5f33 af13 io295nb5f33 ap4 io295pb5f33 ar4 io296nb5f33 ag12 io296pb5f33 af12 io297nb5f33 am11 io297pb5f33 am12 io298nb5f33 ak12 io298pb5f33 al12 io299nb5f33 an11 io299pb5f33 an12 io300nb5f33 an5 io300pb5f33 an6 io301nb5f33 at6 io301pb5f33 at7 io302nb5f34 ah11 io302pb5f34 ah12 io303nb5f34 at4 io303pb5f34 at5 io304nb5f34 aj10 io304pb5f34 aj11 io305nb5f34 am10 io305pb5f34 an10 io306nb5f34 ak10 io306pb5f34 al10 io307nb5f34 ap6 io307pb5f34 ap7 io308nb5f34 ak9 io308pb5f34 al9 io309nb5f34 ar6 io309pb5f34 ar7 io310nb5f34 ah9 io310pb5f34 ah10 io311nb5f34 am8 1272-pin ccga/lga rtax4000s/sl function pin number io311pb5f34 am7 io312nb5f34 ag9 io312pb5f34 ag8 io313nb5f34 an7 io313pb5f34 an8 bank 6 io314nb6f36 af8 io314pb6f36 af9 io315nb6f36 an2 io315pb6f36 an3 io316nb6f36 ah4 io316pb6f36 aj4 io317nb6f36 al3 io317pb6f36 al4 io318nb6f36 ak4 io318pb6f36 ak5 io319nb6f36 ae10 io319pb6f36 ae9 io320nb6f36 ag4 io320pb6f36 ag5 io321nb6f36 ae11 io321pb6f36 ad11 io322nb6f37 ag3 io322pb6f37 ah3 io323nb6f37 ag7 io323pb6f37 ag6 io324nb6f37 ah7 io324pb6f37 ah6 io325nb6f37 aj5 io325pb6f37 ah5 io326nb6f37 ak2 io326pb6f37 ak3 io327nb6f37 ae7 io327pb6f37 ae8 io328nb6f37 am4 io328pb6f37 an4 io329nb6f37 ad9 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-64 v5.4 io329pb6f37 ad10 io330nb6f37 am1 io330pb6f37 an1 io331nb6f38 ae5 io331pb6f38 ae6 io332nb6f38 af4 io332pb6f38 af5 io333nb6f38 ad8 io333pb6f38 ad7 io334nb6f38 ag2 io334pb6f38 ah2 io335nb6f38 ac12 io335pb6f38 ad12 io336nb6f38 aj1 io336pb6f38 ak1 io337nb6f38 ac8 io337pb6f38 ac9 io338nb6f38 ad3 io338pb6f38 ae3 io339nb6f38 ad5 io339pb6f38 ad6 io340nb6f39 ad4 io340pb6f39 ae4 io341nb6f39 ab8 io341pb6f39 ab9 io342nb6f39 ag1 io342pb6f39 ah1 io343nb6f39 aa12 io343pb6f39 ab12 io344nb6f39 ad2 io344pb6f39 ae2 io345nb6f39 aa11 io345pb6f39 ab11 io346nb6f39 ae1 io346pb6f39 af1 io347nb6f39 al1 io347pb6f39 al2 1272-pin ccga/lga rtax4000s/sl function pin number io348nb6f39 ac4 io348pb6f39 ac5 io349nb6f40 ab6 io349pb6f40 ab7 io350nb6f40 ac1 io350pb6f40 ad1 io351nb6f40 aa9 io351pb6f40 aa10 io352nb6f40 ab2 io352pb6f40 ab3 io353nb6f40 aa7 io353pb6f40 aa8 io354nb6f40 aa2 io354pb6f40 aa3 io355nb6f40 aa5 io355pb6f40 aa6 io356nb6f40 ab4 io356pb6f40 ab5 io357nb6f40 w12 io357pb6f40 y12 io358nb6f41 aa1 io358pb6f41 ab1 io359nb6f41 y8 io359pb6f41 y9 io360nb6f41 y4 io360pb6f41 aa4 io361nb6f41 u12 io361pb6f41 v12 io362nb6f41 w1 io362pb6f41 y1 io363nb6f41 w6 io363pb6f41 w7 io364nb6f41 w5 io364pb6f41 y5 io365nb6f41 w10 io365pb6f41 w9 io366nb6f41 v2 1272-pin ccga/lga rtax4000s/sl function pin number io366pb6f41 w2 bank 7 io367nb7f42 v8 io367pb7f42 w8 io368nb7f42 v3 io368pb7f42 w3 io369nb7f42 v9 io369pb7f42 v10 io370nb7f42 u1 io370pb7f42 v1 io371nb7f42 v7 io371pb7f42 v6 io372nb7f42 u5 io372pb7f42 v5 io373nb7f42 u9 io373pb7f42 u8 io374nb7f42 r1 io374pb7f42 t1 io375nb7f42 t11 io375pb7f42 t12 io376nb7f43 t4 io376pb7f43 u4 io377nb7f43 t8 io377pb7f43 t7 io378nb7f43 t3 io378pb7f43 t2 io379nb7f43 t5 io379pb7f43 t6 io380nb7f43 r5 io380pb7f43 r4 io381nb7f43 r6 io381pb7f43 r7 io382nb7f43 n1 io382pb7f43 p1 io383nb7f43 t10 io383pb7f43 t9 io384nb7f43 r3 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-65 io384pb7f43 r2 io385nb7f44 r12 io385pb7f44 r11 io386nb7f44 l1 io386pb7f44 m1 io387nb7f44 g2 io387pb7f44 f2 io388nb7f44 p5 io388pb7f44 p4 io389nb7f44 r8 io389pb7f44 r9 io390nb7f44 j1 io390pb7f44 k1 io391nb7f44 n12 io391pb7f44 p12 io392nb7f44 m2 io392pb7f44 n2 io393nb7f44 p9 io393pb7f44 p8 io394nb7f45 m3 io394pb7f45 n3 io395nb7f45 m11 io395pb7f45 n11 io396nb7f45 m4 io396pb7f45 n4 io397nb7f45 n5 io397pb7f45 n6 io398nb7f45 j2 io398pb7f45 k2 io399nb7f45 n8 io399pb7f45 n7 io400nb7f45 g1 io400pb7f45 h1 io401nb7f45 m5 io401pb7f45 m6 io402nb7f45 e1 io402pb7f45 f1 1272-pin ccga/lga rtax4000s/sl function pin number io403nb7f46 n10 io403pb7f46 n9 io404nb7f46 l5 io404pb7f46 l4 io405nb7f46 m7 io405pb7f46 m8 io406nb7f46 g3 io406pb7f46 f3 io407nb7f46 m10 io407pb7f46 m9 io408nb7f46 d4 io408pb7f46 d3 io409nb7f46 j7 io409pb7f46 j6 io410nb7f46 j3 io410pb7f46 k3 io411nb7f46 l8 io411pb7f46 l9 io412nb7f47 k5 io412pb7f47 k4 io413nb7f47 k7 io413pb7f47 k6 io414nb7f47 e4 io414pb7f47 f4 io415nb7f47 g4 io415pb7f47 g5 io416nb7f47 h4 io416pb7f47 j4 io417nb7f47 d2 io417pb7f47 d1 io418nb7f47 k8 io418pb7f47 k9 io419nb7f47 h5 io419pb7f47 j5 dedicated i/o gnd j8 gnd aa13 1272-pin ccga/lga rtax4000s/sl function pin number gnd aa15 gnd aa17 gnd aa19 gnd aa21 gnd aa23 gnd aa24 gnd ab14 gnd ab16 gnd ab18 gnd ab20 gnd ab22 gnd ac11 gnd ac13 gnd ac15 gnd ac17 gnd ac19 gnd ac21 gnd ac23 gnd ac24 gnd ac26 gnd ac3 gnd ac30 gnd ac34 gnd ac7 gnd ad13 gnd ad14 gnd ad16 gnd ad18 gnd ad19 gnd ad21 gnd ad23 gnd ad24 gnd ae15 gnd ae25 gnd af10 gnd af11 gnd af14 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-66 v5.4 gnd af17 gnd af20 gnd af23 gnd af26 gnd af27 gnd af3 gnd af30 gnd af34 gnd af7 gnd aj29 gnd aj3 gnd aj30 gnd aj34 gnd aj7 gnd ak11 gnd ak14 gnd ak17 gnd ak20 gnd ak23 gnd ak26 gnd ak29 gnd ak6 gnd ak8 gnd al18 gnd al31 gnd al7 gnd am3 gnd am34 gnd ap11 gnd ap14 gnd ap17 gnd ap2 gnd ap20 gnd ap23 gnd ap26 gnd ap29 gnd ap32 1272-pin ccga/lga rtax4000s/sl function pin number gnd ap35 gnd ap5 gnd ap8 gnd ar3 gnd ar34 gnd b3 gnd b34 gnd c11 gnd c14 gnd c17 gnd c2 gnd c20 gnd c23 gnd c26 gnd c29 gnd c32 gnd c35 gnd c5 gnd c8 gnd e3 gnd e34 gnd f30 gnd f7 gnd g11 gnd g14 gnd g17 gnd g20 gnd g23 gnd g26 gnd g29 gnd g8 gnd h3 gnd h30 gnd h34 gnd h7 gnd j31 gnd l10 1272-pin ccga/lga rtax4000s/sl function pin number gnd l11 gnd l14 gnd l17 gnd l20 gnd l23 gnd l26 gnd l27 gnd l3 gnd l30 gnd l34 gnd l7 gnd m15 gnd m25 gnd n14 gnd n16 gnd n18 gnd n19 gnd n21 gnd n23 gnd n24 gnd p11 gnd p13 gnd p14 gnd p16 gnd p18 gnd p20 gnd p22 gnd p24 gnd p26 gnd p3 gnd p30 gnd p34 gnd p7 gnd r15 gnd r17 gnd r19 gnd r21 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-67 gnd r23 gnd r27 gnd t13 gnd t14 gnd t16 gnd t18 gnd t20 gnd t22 gnd t24 gnd u11 gnd u15 gnd u17 gnd u19 gnd u21 gnd u23 gnd u26 gnd u3 gnd u30 gnd u34 gnd u7 gnd v13 gnd v14 gnd v16 gnd v18 gnd v20 gnd v22 gnd v24 gnd v33 gnd v4 gnd w11 gnd w13 gnd w15 gnd w17 gnd w19 gnd w21 gnd w23 gnd w24 1272-pin ccga/lga rtax4000s/sl function pin number gnd w26 gnd w4 gnd y11 gnd y14 gnd y16 gnd y18 gnd y20 gnd y22 gnd y26 gnd y3 gnd y30 gnd y34 gnd y7 nc aj8 nc w36 pra f18 prb a18 prc al19 prd at19 tck h8 tdi f6 tdo h9 tms f5 trst g7 v cca a19 v cca aa14 v cca aa16 v cca aa18 v cca aa20 v cca aa22 v cca ab15 v cca ab17 v cca ab19 v cca ab21 v cca ab23 v cca ac14 v cca ac16 1272-pin ccga/lga rtax4000s/sl function pin number v cca ac18 v cca ac20 v cca ac22 v cca ae12 v cca al32 v cca al5 v cca ap3 v cca ap34 v cca at18 v cca c3 v cca c34 v cca j30 v cca m12 v cca p15 v cca p17 v cca p19 v cca p21 v cca p23 v cca r14 v cca r16 v cca r18 v cca r20 v cca r22 v cca t15 v cca t17 v cca t19 v cca t21 v cca t23 v cca u14 v cca u16 v cca u18 v cca u20 v cca u22 v cca v15 v cca v17 v cca v19 v cca v21 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas 3-68 v5.4 v cca v23 v cca w14 v cca w16 v cca w18 v cca w20 v cca w22 v cca w33 v cca y15 v cca y17 v cca y19 v cca y21 v cca y23 v ccda ab10 v ccda ab27 v ccda ae22 v ccda af18 v ccda af19 v ccda ah29 v ccda ah8 v ccda aj28 v ccda aj9 v ccda ak30 v ccda ak7 v ccda al30 v ccda al6 v ccda am13 v ccda am24 v ccda am31 v ccda am32 v ccda am5 v ccda am6 v ccda an16 v ccda an21 v ccda ap16 v ccda ap21 v ccda c16 v ccda c21 1272-pin ccga/lga rtax4000s/sl function pin number v ccda d16 v ccda d21 v ccda e13 v ccda e24 v ccda e5 v ccda e6 v ccda f19 v ccda f31 v ccda g30 v ccda g31 v ccda g6 v ccda h28 v ccda h29 v ccda j29 v ccda l18 v ccda l19 v ccda m22 v ccda n13 v ccda r10 v ccda v11 v ccda v26 v cci b0 b11 v cci b0 b14 v cci b0 b17 v cci b0 b5 v cci b0 b8 v cci b0 f11 v cci b0 f14 v cci b0 f17 v cci b0 f8 v cci b0 k11 v cci b0 k14 v cci b0 k17 v cci b0 n15 v cci b0 n17 v ccib 1 b20 v ccib 1 b23 1272-pin ccga/lga rtax4000s/sl function pin number v ccib 1 b26 v ccib 1 b29 v ccib 1 b32 v ccib 1 f20 v ccib 1 f23 v ccib 1 f26 v ccib 1 f29 v ccib 1 k20 v ccib 1 k23 v ccib 1 k26 v ccib 1 n20 v ccib 1 n22 v cci b2 e35 v cci b2 h31 v cci b2 h35 v cci b2 k27 v cci b2 l31 v cci b2 l35 v cci b2 p27 v cci b2 p31 v cci b2 p35 v cci b2 r24 v cci b2 u24 v cci b2 u27 v cci b2 u31 v cci b2 u35 v cci b3 ab24 v cci b3 ac27 v cci b3 ac31 v cci b3 ac35 v cci b3 af31 v cci b3 af35 v cci b3 ag27 v cci b3 aj31 v cci b3 aj35 v cci b3 am35 v cci b3 y24 1272-pin ccga/lga rtax4000s/sl function pin number
rtax-s/sl radtolerant fpgas v5.4 3-69 v cci b3 y27 v cci b3 y31 v cci b3 y35 v cci b4 ad20 v cci b4 ad22 v cci b4 ag20 v cci b4 ag23 v cci b4 ag26 v cci b4 al20 v cci b4 al23 v cci b4 al26 v cci b4 al29 v cci b4 ar20 v cci b4 ar23 v cci b4 ar26 v cci b4 ar29 v cci b4 ar32 v cci b5 ad15 v cci b5 ad17 v cci b5 ag11 1272-pin ccga/lga rtax4000s/sl function pin number v cci b5 ag14 v cci b5 ag17 v cci b5 al11 v cci b5 al14 v cci b5 al17 v cci b5 al8 v cci b5 ar11 v cci b5 ar14 v cci b5 ar17 v cci b5 ar5 v cci b5 ar8 v cci b6 ab13 v cci b6 ac10 v cci b6 ac2 v cci b6 ac6 v cci b6 af2 v cci b6 af6 v cci b6 ag10 v cci b6 aj2 v cci b6 aj6 1272-pin ccga/lga rtax4000s/sl function pin number v cci b6 am2 v cci b6 y10 v cci b6 y13 v cci b6 y2 v cci b6 y6 v cci b7 e2 v cci b7 h2 v cci b7 h6 v cci b7 k10 v cci b7 l2 v cci b7 l6 v cci b7 p10 v cci b7 p2 v cci b7 p6 v cci b7 r13 v cci b7 u10 v cci b7 u13 v cci b7 u2 v cci b7 u6 v pump f32 1272-pin ccga/lga rtax4000s/sl function pin number

rtax-s/sl radtolerant fpgas v5.4 4-1 datasheet information list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v5 . 4) page v5.3 (october 2008) rt4000s now supports the low-power grade option. in addition, this device has moved from a preliminary state to a production state. n/a rtax250s/sl supports 624-ccga/lga. the following tables were updated. "rtax-s/sl family product profile" , "temperature grade offerings" , "ordering information" n/a all dc input and output tables and timing characteristic tables were updated. n/a the "ordering information" section was updated. b was deleted from the package type and the speed grade description was updated. ii the "temperature grade offerings" table note was updated. ii the "speed grade and temperature grade matrix" table was updated. iii the "i/os per package" table is new. iii in table 2 ? actel mil-std-883 class b product flow for rtax-s/sl1, 2 , "tbd" in step 4 was changed to "condition a". iv in table 3 ? actel extended flow for rtax-s/sl1, 2, 3, 4 , "tbd" in step 4 was changed to "condition a". v in the first paragraph of the "general description" section , it originally said there were two million equivalent system gates but that is incorrect beca use there are four million equivalent system gates. 1-1 information about segmenting clocks was added to the "global resources" section . 1-7 the "prototyping with proasic3e reprogrammable units" section is new. 1-8 in table 2-1 ? i/o features comparison , lvttl was updated. note 1 was updated and note 4 is new. 2-1 in table 2-2 ? absolute maximum ratings , the limit for v i was changed from 4.0 to 4.1 and v pump was added to the table. 2-2 the "5 v tolerance" section was significantly updated. 2-1 rtax4000s/sl data was updated in table 2-4 ? rtax-s standby current . for rtax2000s/sl, i ccdiffa was changed from 2.96 to 3.13. the i il /i ih heading was changed to i ih , i il , or i oz . note 1 is new. 2-3 rtax4000s/sl data was added to table 2-5 ? rtax-sl standby current . i cca data was updated for typical 25c for rt ax2000s/sl, rtax1000s/sl, and rtax250s/sl. the i il /i ih heading was changed to i ih , i il , or i oz . note 1 is new. 2-3 table 2-6 ? default cload / vcci was significantly updated. 2-4 in the "ptotal = pdc + pac" section , the "pdc" definition, n banks was deleted. 2-5 in the "pmemory = 0 mw" section , the "pdc" definition, n banks was deleted. 2-6 table 2-8 ? package thermal characteristics was updated to include 624-pin ccga/lga 2-7 table 2-9 ? temperature and voltage timing derating factors was significantly updated. 2-9 in the "hardwired clock" section , the clock-to-out (pad-to-pad) was updated. t rco was changed from 0.9 to 0.96. 2-10 in the "routed clock1" section , the clock-to-out (pad-to-pad) was updated. t rco was changed from 0.9 to 0.96. footnote 1 is new. 2-10 the "vccibx supply voltage" section was updated to include information about unused banks. 2-11 the "hclka/b/c/d dedicated (hardwired) clocks a, b, c, and d" section was updated. 2-11 the "vpump supply voltage (external pump)" section was updated. 2-11
rtax-s/sl radtolerant fpgas 4-2 v5.4 v5.3 (continued) the "clke/f/g/h global clocks e, f, g, and h" section was updated. 2-11 the "pra/b/c/d probes a, b, c, and d" section was updated. 2-12 information about seus and cell buffers was added to "introduction" section . 2-12 in table 2-15 ? macros for single-ended i/o standards , the macro names for lvttl were changed from _h_ to _f_ 2-19 the "customizing the i/o" section was updated. table 2-14 ? bank wide delay values is new. 2-14 the data in table 2-19 ? i/o weak pull-up/pull-down resistances1 was significantly updated. notes 1, 2, and 3 were also updated. 2-22 the note was updated to include pin compatibility information for "352-pin cqfp" . 3-8 the note was updated to include pin compatibility information for "624-pin ccga/lga" . the rtax250s/sl pin table is new. 3-26 the "352-pin cqfp" table for the rtax250s/sl device is new. 3-10 in table 2-21 ? dc input and output levels , the footnote is new. 2-26 in table 2-36 ? worst-case military conditions vcca = 1.4 v, vcci = 3.0 v, tj = 125c , the footnote is new. 2-51 table 2-54 ? worst-case military conditions vcca = 1.4 v, vcci = 3.0 v, tj = 125c was significantly updated. 2-57 table 2-88 ? one ram block (worst-case military conditions vcca = 1.4 v, vcci = 3.0 v, tj = 125c) to table 2-92 ? sixteen ram blocks are cascaded (w orst-case military conditi ons vcca = 1.4 v, vcci = 3.0 v, tj = 125c) were updated. 2-85 to 2-89 table 2-96 ? fifo signal description to table 2-101 ? sixteen fifo bloc ks are cascaded (worst-case military conditions vcca = 1.4 v, vcci = 3.0 v, tj = 125c) were updated. 2-94 to 2-98 in the "rtax2000s/sl function" table , the block numbers were remove d. for example "bank 0, block 0" was changed to "bank 0". 3-5 v5.2 (october 2007) in table 2-5 ? rtax-sl standby current , the i cca specifications were updated for 125c. 2-3 v5.1 (august 2007) the "i/o logic" section was updated to include information about user flip-flops being immune to seu. 1-5 the "low-cost prototyping solutions" section was updated significantly. 1-7 table 2-4 ? rtax-s standby current was updated to include i ih /i il . 2-3 table 2-5 ? rtax-sl standby current was updated to include i ih /i il . 2-3 the cg1272 was updated in the "package thermal characteristics" table . 2-7 the temperature in note 1 was changed from 175 to 125 in the "temperature and voltage timing derating factors" table . 2-9 in the "timing model" , the hardwired clock was changed to routed or hardwired. 2-10 v5.0 (june 2007) the "ordering information" section was updated to include the sigma six column and bae column designation. a note was added to the "temperature grade offerings" table regarding the sigma six column and bae column. ii previous version changes in current version (v5 . 4) page
rtax-s/sl radtolerant fpgas v5.4 4-3 v4.0 (may 2007) rtax-sl information is new. n/a ev flow (class v flow equivalent processing) information is new. n/a the "ordering information" section was updated. ii the "actel mil-std-883 class b product flow" table was updated. iv the "actel extended flow" table was updated. v the "low-cost prototyping solutions" section was updated to include rtax-sl prototyping information. 1-7 table 2-5 ? rtax-sl standby current is new. 2-3 in the "sample case 2: convection = 0" section , cb was changed to t j . 2-8 the axcelerator figure listed below the "vccda supply voltage" section was incorrect and has been removed from the datasheet. 2-11 the "256-pin cqfp" table for the rtax2000s/sl device is new. 3-5 v3.0 september 2006 all information regarding the rtax4000s device is new. n/a the "timing model" was updated. 2-10 the "specifications" section was updated. i the sel and set informat ion was updated in the "designed for space" section .i the maximum i/o counts for the rtax250s and rtax1000s were updated in table 1 ? rtax-s/sl family product profile . i the "device resources" table was updated for cg1272/lg1272. iii the rtax-s/sl testing and reliability update white paper was added to the "white papers" section . 1-9 the "user i/os" section was updated with information on configuring unused i/os. 2-12 implementing ddr was updated in the "using ddr (double data rate)" section . 2-17 pset was changed to pre and d was changed to e in figure 2-6 ? ddr register . 2-18 v3.0 the "jtag" section was updated with jt ag pin information. 2-100 (continued) figure 2-1 ? use of an external resistor for 5 v tolerance was updated. 2-1 note 2 in table 2-2 ? absolute maximum ratings was updated. 2-2 the "calculating power dissipation" section was updated. 2-3 table 2-25 ? worst-case military conditions vcca = 1.4 v, vcci = 2.3 v, tj = 125c was updated. 2-30 the "hardwired clock" and "routed clock1" equations were updated. 2-10 table 2-4 ? rtax-s standby current was updated. 2-3 table 2-6 ? default cload / vcci was updated. 2-4 table 2-9 ? temperature and voltage timing derating factors was updated. 2-9 all timing characteristic tables were updated. n/a the "352-pin cqfp" table for the rtax4000s is new. 3-22 the "1272-pin ccga/lga" table for the rtax4000s is new. 3-58 v2.2 may 2006 all timing characteristic tables were updated. n/a cold sparing was added to th e hot insertion heading in table 2-1 ? i/o features comparison . 2-1 the "thermal characteristics" section was updated. 2-7 the "simultaneous switching outputs (sso)" section was updated. 2-14 the "timing model" has been updated. 2-10 previous version changes in current version (v5 . 4) page
rtax-s/sl radtolerant fpgas 4-4 v5.4 v2.2 (continued) the "hardwired clock" and "routed clock1" equations were updated. 2-10 table 2-6 ? default cload / vcci was updated. 2-4 table 2-18 ? i/o weak pull-up/pull-down resistances 1 is new. 2-21 a note was added to table 2-58 ? dc input and output levels . 2-60 v2.1 october 2005 the lvds capable i/o specification was added to "leading-edge performance" . i-i table 1 ? rtax-s/sl family product profile was updated to include cq256. i-i cq256 was added to the "temperature grade offerings" table. i-ii cq256 is new and cq352 for the rtax1000s device was updated in the "device resources" table. i-iii the "overshoot/undershoot limits" section is new. 2-2 table 2-2 ? absolute maximum ratings was updated. 2-2 table 2-3 ? rtax-s/sl recomme nded operating conditions was updated. 2-2 the "timing model" has been updated. 2-10 the "hardwired clock" and "routed clock1" equations were updated. 2-10 this sentence was updated in the "clke/f/g/h global clocks e, f, g, and h" section: when the clk pins are unused, actel recommen ds that they are tied to a known state. 2-11 figure 2-27 ? lvpecl circuit was updated. the following labels were corrected: inbuf_lvpecl outbuf_lvpecl 2-60 the following sentence was removed from "global resource distribution" : an unused input can be tied to ground for power savings. 2-78 the "ram" section was updated. 2-81 the "256-pin cqfp" package figure and is new. 3-4 v2.0 in ta b l e 2 - 4 , the i cca column heading was changed to i ccda and note 3 is new. 2-3 previous version changes in current version (v5 . 4) page
rtax-s/sl radtolerant fpgas v5.4 4-5 advanced v0.5 the "designed for space" section was updated. i-i ta b l e 1 was updated to include 1152 ccga/lga. i-i the "temperature grade offerings" table was updated to include the 1152 ccga. i-iii the rtax1000s and the rtax2000s columns were updated in the "device resources" table. i-iii figure 1-9 was updated and a note was added to the figure. 1-8 table 2-4 ? rtax-s standby current was updated. 2-3 in ta b l e 2 - 4 the lvpecl and lvds specifications were u pdated. a note was also added to the table. 2-3 the "global resource access macros" section was updated. 2-80 the "jtag" section was updated. 2-100 in the "data registers (drs)" section the idcode and usercode were changed from 32 bits to 33 bits. 2-100 150c was changed to 125c in the "thermal characteristics" section. 2-7 table 2-8 ? package thermal characteristics was updated to include the 1152 ccga. values in the table were updated. 2-7 a note was added to the "fifo" section. 2-90 table 2-7 ? different components contributing to the total power consumption in rtax-s/sl devices was updated. 2-4 ta b l e 2 - 1 7 was updated. 2-20 all timing characteristic tables from ta b l e 2 - 2 2 to ta b l e 2 - 8 4 were updated. 2-25 to 2-81 in the "actel mil-std-883 class b product flow" table, #3 for the 883 method was updated. a note was also added to the table. i-iv in the "actel extended flow" table, #5 for the method column was updated. the notes were also added to the table. i-iv in the "pin descriptions" section, the descriptions for the "hclka/b/c/d dedicated (hardwired) clocks a, b, c, and d" and "clke/f/g/h global clocks e, f, g, and h" were updated. 2-11 a footnote was added to the "pra/b/c/d probes a, b, c, and d" , "tck2 test clock" , "tdi2 test data input" , "tdo2 test data output" , and "tdo2 test data output" descriptions. 2-12 the "1152-pin ccga/lga" section is new. 3-45 advanced v0.4 let th values for seu and sel updated under "designed for space" .i-i "ordering information" was updated/ the "temperature grade offerings" , "speed grade and temperature grade matrix" tables are new and the "device resources" was updated. i-ii sections "actel mil-std-883 class b product flow" and "actel extended flow" are new. i-iv , i-v "general description" was updated. 1-1 table 2-7 ? different components contributing to the total power consumption in rtax-s/sl devices was updated. 2-4 the "thermal characteristics" section was updated. 2-7 figure 2-4 ? timing model , the "hardwired clock" section and the "routed clock1" section were updated. 2-10 previous version changes in current version (v5 . 4) page
rtax-s/sl radtolerant fpgas 4-6 v5.4 advanced v.04 (continued) the "introduction" section under "user i/os" was updated to give details regarding v ref usage. 2-12 the "simultaneous switching outputs (sso)" section under "user i/os" was updated. 2-14 "using ddr (double data rate)" is new. 2-17 ta b l e 2 - 1 8 was updated. 2-22 all timing characteristic tables were updated. 2-25 to 2-99 "introduction" was updated. 2-66 the "seu hardened d flip-flop (dff)" section was moved under "r-cell" and updated. 2-67 the "global resource distribution" section is new. 2-78 the "enhancing seu performance" section is new. 2-83 figure 2-49 and figure 2-50 were updated. 2-84 figure 2-57 and figure 2-58 were updated. 2-95 the "charge pump bypass" section is new. 2-100 the "trst" section was updated. 2-100 the "global set fuse" section is new. 2-102 the "208-pin cqfp" for both the rtax250s and rtax1000s were added. 3-1 the "352-pin cqfp" pin tables for both the rtax1000s and rtax2000s were updated. 3-8 the "624-pin ccga/lga" pin tables for both the rtax1000s and rtax2000s were updated. 3-26 advanced v0.3 the "designed for space" section was updated. i-i a new device, the rtax250s, was added to the "designed for space" , "ordering information" , "temperature grade offerings" and "device resources" sections. i to iii 2.5v gtl+ support across full military range was removed. n/a table 1-1 ? number of core tiles per device was updated. 1-4 table 2-4 ? rtax-s standby current and table 2-6 ? default cload / vcci were updated. 2-4 table 2-7 ? different components contributing to the total power consumption in rtax-s/sl devices was updated. 2-4 table 2-13 ? legal i/o usage matrix was updated. 2-15 table 2-17 ? i/o macros for voltage-referenced i/o standards 2-20 advanced v0.2 in the "352-pin cqfp" for the rtax1000s, pin 80 has been changed from vcci to vccib6. 3-14 in the "208 cqfp" and "352-pin cqfp" , the nc (v pp ) was changed to nc for all pins. 3-2 to 3-14 advanced v0.1 the 352-pin cqfp for the rtax1000s is new. 3-10 pins 14 and 32 have been changed from vcca to vcci for th e rtax2000s in the "352-pin cqfp" . 3-10 the "624-pin ccga/lga" for the rtax1000s is new. 3-39 previous version changes in current version (v5 . 4) page
rtax-s/sl radtolerant fpgas v5.4 4-7 datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as ?product brief,? ?advance d,? ?production,? and ?datasheet supplement.? the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. international traffic in arms regulations (itar) the product described in this datasheet are subject to the international traf fic in arms regulations (itar). they require an approved export license prior to export from th e united states. an export in cludes release of product or disclosure of technology to a foreign nati onal inside or outsid e the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product intr oduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-relia bility applications. con sult actel?s terms an d conditions for specif ic liability exclusions relating to life-support applic ations. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/documents /ort_report.pdf. actel also offers a variety of enhanced qualification and lot acceptance screening procedures. c ontact your local actel sales office for additional reliability information.
5172169-12/5.09 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court, meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu building 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel is the leader in low-power and mixed-signal fp gas and offers the most comprehensive portfolio of system and power management solutions. po wer matters. learn more at www.actel.com.

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